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| 4.25 gbps 40 40 digital crosspoint switch data sheet adn4605 features dc to 4.25 gbps per port nrz data rate adjustable receive equalization 3 db, 6 db, or 12 db boost compensates over 40 inches of fr4 at 4.25 gbps adjustable transmit preemphasis /de emphasis programmable boost and output level compensates over 4 0 inches of fr4 at 4.25 gbps low p ower 1 05 mw per channel at 2.5 v (400 mv p - p differential output level swing ) 40 40, fully differential, non blocking array double rank connection programming with dual maps low jitter, typically < 25 ps flexible 2.5 v to 3.3 v supply range dc - or ac - coupled differential pecl/ cml inputs differential cml output s per - l ane polarity inversion for routing ease 50 ? on - chip i/o termination with disable feature supports 8b10b, scrambled or uncoded nrz data serial (i?c slave or spi) control interface parallel control interface functional block dia gram eq rx tx pre- emphasis 40 40 switch ma trix connection ma p 1 connection ma p 0 p arallel/seria l contro l logic inter f ace pre- emphasis leve l settings output leve l settings adn4605 v cc v ee dv cc op[39:0] v tt oa , v tt ob on[39:0] ip[39:0] v tti a , v ttib in[39:0] i 2 c/spi (upd a te) sdi/re scl/sck/ we reset ser/ p ar cs equaliz a tion settings dat a[1] (upd a te) dat a[0]/ sda/sdo dat a[7:2] addr[7:0] 09796-001 figure 1 . applications digital video (hdmi, dvi, displayport, 3g/hd/sd - sdi) fiber optic network switching high speed serial backplane routing to o c - 48 with fec xaui, 4x fibre channel, infiniband ? , and gbe over backplane data storage network s general description the adn4605 is a 40 40 asynchronous, protocol agnostic, digital crosspoint switch, with 40 differential pecl/cml - compatible inputs and 40 differential programmable cml outputs. the adn4605 is optimized for nrz signaling with data rates of up to 4.25 gbps per port. each port offers adjustable level s of input equalization, programmable output swing, and output preemphasis /deemphasis . the adn4605 non block ing switch core implements a 40 40 crossbar and supports independent channel switching through seri al and parallel control interfaces. the adn4605 has low latency and very low channel - to - channel skew. an i 2 c , spi, or p arallel i nterface is used to communicate with the device for control of connectivity and o ther features. the adn4605 is assembled in a 35 mm 35 mm, 352 bga package and operates over a temperature range of ? 40c to +85c . rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are th e property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 anal og devices, inc. all rights reserved.
adn4605 data sheet rev. a | page 2 of 56 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical specifications ............................................................... 3 i 2 c timing specifications ............................................................ 5 spi timing specifications ........................................................... 5 parallel mode specifications ....................................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performanc e characteristics ........................................... 18 theory of operation ...................................................................... 24 introduction ................................................................................ 24 rece ivers ...................................................................................... 25 polarity inversion ....................................................................... 26 switch core ................................................................................. 27 reset ............................................................................................. 28 transmitters ................................................................................ 29 termination ................................................................................. 32 i 2 c serial control interface ........................................................... 33 i 2 c dat a wr ite ............................................................................. 33 i 2 c data read .............................................................................. 34 spi serial control interface .......................................................... 35 parallel control interface .............................................................. 38 address inputs: addr[7:0] ...................................................... 38 data inputs/ outputs: data[7:0] ............................................. 38 write operation .......................................................................... 38 read operation ........................................................................... 38 regis ter map ................................................................................... 39 applications information .............................................................. 49 supply sequencing ..................................................................... 51 powe r dissipation ....................................................................... 51 output compliance ................................................................... 51 tx/xpt headroom ............................................................. 51 printed circuit board (pcb) layout guidelines ................... 54 outline dimensions ....................................................................... 55 ordering guide ............................................................................... 55 revision hist ory 11/ 11 rev. 0 to rev. a changes to printed circuit board (pcb) layout guidelines ........................................................................................ 54 removed figure 55, renumbered sequentially .......................... 54 6/11 rev ision 0: initial version data sheet adn4605 rev. a | page 3 of 56 specifications electrical specifica tions v cc = 2.5 v, v tti x = 2.5 v, v tto x = 2.5 v, d v cc = 3.3 v, v ee = 0 v, r l = 50 ? , output level ( olev ) = 4 (16 ma), preempha s is ( pe ) = 0 (0 db ), equalizer ( eq ) = 1 (3 db), data rate = 4.25 gbps (prbs7 data pattern) , ac - coupled inputs and outputs, differential input swing = 800 mv p - p, t a = 2 5 c, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance data rate (dr) per channel (nrz) dc 4.25 gbps deterministic jitter data rate 4.25 gbps, no channel 2 0 ps p - p random jitter rms, no channel 0.8 ps rms resi dual deterministic jitter with receive equalization data rate = 4.25 gbps, 20 in. fr4, eq boost = 12 db 14 ps p - p data rate = 4.25 gbps, 30 in. fr4, eq boost = 12 db 15 ps p - p data rate = 4.25 gbps, 40 in. fr4, eq boost = 12 db 25 ps p - p residu al deterministic jitter with transmit preemphasis data rate = 4.25 gbps, 20 in. fr4, pe boost = 5.6 db 22 ps p - p data rate = 4.2 5 gbps, 30 in. fr4, pe boost = 6.8 db 28 ps p - p data rate = 4.2 5 gbps, 40 in. fr4, pe boost = 9.5 db 32 ps p - p propa gation delay input to output 920 ps channel -to - channel skew earliest input/output lane to latest input/output lane 200 ps switching time update logic switching to 50% output data 20 ns output rise/fall time 20% to 80% 108 ps input characterist ics minimum differential input voltage swing 1 v icm = v cc ? 0.6 v 50 mv p - p diff maximum differential input voltage swing 1 v icm = v cc ? 0.6 v 2000 mv p - p diff input voltage range single - ended absolute voltage level, v l v ee + 1. 0 v single - end ed absolute voltage level, v h v cc + 0.3 v output characteristics output voltage swing differential, pe boost = 0 db, default output level, at dc 670 800 875 mv p - p diff output voltage range single - ended absolute voltage level, v l v cc C 1.4 v s ingle - ended absolute voltage level, v h v cc + 0.3 v per - port output current pe boost = 0 db, default output level 16 ma pe boost = 6 db, default output level 32 ma termination characteristics resistance differential, v cc = v min to v max , t a = t min to t max 88 100 114 ? temperature coefficient 0.015 ? / c power supply operating range v cc v ee = 0 v 2.25 2.5 3.6 v dv cc v ee = 0 v 3.0 3.3 3.6 v v tti a , v tti b v ee = 0 v 2.5 v cc + 0.3 v v ttoa , v tto b v ee = 0 v 2.5 v cc + 0.3 v supply current inputs/ outputs disabled (reset condition) i cc 55 64 m a i dvcc 0.3 1.1 m a i tti a + i tti b inputs floating 0 1.5 ma i tto a + i tto b outputs floating 0 1.5 ma adn4605 data sheet rev. a | page 4 of 56 parameter conditions min typ max unit supply current all outputs enabled, ac - coupled i/o, 200 mv i/o swings (400 mv p -p differential), pe boost = 0 db, 50 ? far - end terminations i cc 1320 1410 m a i dvcc 0.3 1.1 ma i tti a + i tti b 11 15 ma i tto a + i tto b 335 360 ma supply current all outputs enabled, ac - coupled i/o, 400 mv i/o swings (800 mv p - p differential), pe boost = 0 db, 50 ? far- end termin ations i cc 137 0 146 0 ma i dvcc 0 . 3 1.1 ma i tti a + i tti b 1 1 15 ma i tto a + i tto b 6 65 7 1 5 ma supply current all outputs enabled, ac - coupled i/o, 400 mv i/o swings (800 mv p - p differential), pe boost = 6 db, 50 ? far- end terminations i cc 1 850 196 0 ma i dvcc 0 . 3 1.1 ma i tti a + i tti b 1 1 15 ma i tto a + i tto b 1 340 138 0 thermal characteristics operating temperature 2 ?40 +85 c ja still air; jedec multi layer test board 11.6 c/w jb 1 m/s air velocity 5.4 c/w jc 1 m /s air velocity 0.72 c/w logic characteristics input high voltage threshold (v ih ) dv cc = 3.3 v 0.7 d v cc v input low voltage threshold (v il ) dv cc = 3.3 v 0. 25 d v cc v output high voltage (v oh ) i oh = ? 3 ma ( i 2 c /spi mode only ) 0.75 dv cc d v cc v output low voltage (v ol ) i ol = +3 ma v ee 0.4 v 1 v icm is the input common - mode voltage. 2 junction temperature cannot exceed 125 c (s ee the absolute maximum ratings section). data sheet adn4605 rev. a | page 5 of 56 i 2 c timing specification s sda scl t f t low t hd;sta t r t hd;dat t high t su;dat t f t su;sta t hd;sta t sp t su;sto t r t buf s p sr s 09796-002 figure 2 . i 2 c timing diagram table 2. i 2 c timing specifications parameter symbol min max unit scl clock frequency f scl 0 500+ khz hold time for a s tart condition t hd; sta 0.5 s setup time for a rep eated s tart condition t su; sta 0.5 s low period of the scl clock t low 1.4 s high period of the scl clock t high 0.6 s data hold time t hd; dat 0.02 s data setu p time t su; dat 0.02 s rise time for both sda and scl t r 1 300 ns fall time for bot h sda and scl t f 1 300 ns setup time for s top condition t su; sto 0.5 s bus free time between a s top condition and a s tart condition t buf 1 ns bus idle time after a reset 20 ns reset pulse width 20 ns spi timing specification s t 1 t 2 t 3 t 5 t 6 t 4 t 7 t 8 d7 cs sclk din dout d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 09796-003 figure 3 . spi timing diagram table 3. spi timing specifications parameter symbol min max unit sck clock frequency f sck 10 mhz cs to sclk setup time t 1 0 ns sclk high pulse width t 2 30 ns sclk low p ulse width t 3 30 ns data access time after sclk falling edge t 4 45 ns data setup time prior to sclk rising edge t 5 10 ns data hold time after sclk rising edge t 6 30 ns cs to sclk hold time t 7 0 ns cs to sdo hi gh impedance t 8 45 ns reset pulse width 20 ns adn4605 data sheet rev. a | page 6 of 56 parallel mode specif ications update 1 0 we d7:d0 a7:a0 1 0 cs 1 0 0 1 t 6 t 8 t 3 t 5 t 1 t 2 t 4 t 7 09796-004 figure 4 . parallel mode write cycle table 4. parallel mode write cycle timing specifications limit parameter symbol mi n typ max unit chip select setup time t 1 0 ns parallel data setup time t 2 0 ns we pulse width t 3 30 50 n s parallel data hold time t 4 25 n s we pulse separation t 5 25 n s we to update delay t 6 40 n s update pulse width t 7 30 n s chip select hold time t 8 0 n s reset pulse width 20 ns 1 0 re cs 1 0 d7:d0 data (addr 1) addr 1 1 0 addr 2 a7:a0 1 0 data (addr 2) t 1 t 2 t 6 t 5 t 3 t 4 09796-005 figure 5 . parallel mode read cycle table 5. parallel mode r ead cycle timing specifications limit parameter symbol min typ max unit chip select setup time t 1 0 n s parallel re setup to valid time t 2 10 ns data access time t 3 25 50 n s address to re hold time t 4 2 5 n s data to re hold time t 5 25 n s chip select hold time t 6 5 n s data sheet adn4605 rev. a | page 7 of 56 absolute maximum rat ings table 6. parameter rating v cc to v ee 3.7 v dv cc to v ee 3.7 v v tti a , v tti b v cc + 0.6 v v tto a , v tto b v cc + 0.6 v internal power dissipation 1 8.4 w differential input voltage 2.0 v logic input voltage v ee C 0.3 v < v in < v cc + 0.6 v storage temperature range ?65c to +125c junction temperature 125c 1 internal power dissipation is for the device in free air. t a = 27 c; ja = 11.6c/w in still air. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution adn4605 data sheet rev. a | page 8 of 56 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af v ee v ee v ee v ee v ee v ee on39 op39 on37 op37 on35 op35 on33 op33 on31 op31 on29 op29 on27 op27 on25 op25 on23 op23 on21 op21 on38 op38 on36 op36 on34 op34 on32 op32 on30 op30 on28 op28 on26 op26 on24 op24 on22 op22 v tt ob v tt ob v tt ob v tt ob v tt ob v tt ob v tt ob v tt ob v tt ob v tt ob v tt ob on20 op20 v ee v ee v ee v ee v ee dv cc dv cc v cc v cc v cc v ttib v ttib v ttib v ttib v cc cs re we v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc ip0 in0 ip1 ip2 in1 in2 ip3 ip4 in3 in4 ip5 ip6 in5 in6 ip7 ip8 in7 in8 ip9 ip10 in9 ip12 in 1 1 in12 ip13 in10 ip 1 1 in14 ip15 ip14 in13 in16 ip17 in18 ip19 ip16 in15 ip18 in17 in19 v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v ee v ee v ee v ee v ee v ee v ee v cc v cc v ee v ee v ee v ee v ee v ee v ee dv cc v ee v tti a v tti a v tti a v tti a v tti a v tti a v tti a v tti a v tti a v tti a v tti a v cc v cc v cc dv cc v ee in38 ip39 ip38 in36 ip36 in37 ip37 in34 ip34 in35 ip35 in32 ip32 in33 ip33 in30 ip30 in31 ip31 v ee v ee v ee in39 in28 ip29 ip28 in26 ip26 in27 ip27 in24 ip24 in25 ip25 in22 ip22 in23 ip23 in20 ip20 in21 ip21 in29 v ee v ee v cc dv cc v cc v cc v ee v ee v ee v ee on19 v ee v ee v ee v ee v ee dat a7 dat a6 dat a5 dat a4 dat a3 dat a2 dat a1 dat a0 v ttib v ttib v ttib v ttib v ttib v ttib v ttib v ee v ee v cc v cc v cc v cc v cc v ee v ee v ee v ee v ee v ee v ee op0 on0 op1 on1 op2 on2 op3 on3 op4 on4 op5 on5 op6 on6 op7 on7 op8 on8 op9 on9 op10 on10 op 1 1 on 1 1 op12 on12 op13 on13 op14 on14 op15 on15 op16 on16 op17 on17 op18 on18 op19 v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee addr7 v tt oa v tt oa v tt oa v tt oa v tt oa v tt oa v tt oa v tt oa v tt oa v tt oa v tt oa addr6 addr5 addr4 addr3 addr2 addr1 addr0 reset ser/ p ar i 2 c/ spi adn4605 t op v iew 09796-006 figure 6 . pin configuration data sheet adn4605 rev. a | page 9 of 56 table 7. pin function descriptions pin no. mnemonic type description a1 v ee power negative supply. a2 v ee power negative supply . a3 v ee power negative supply . a4 on39 output high speed o utput complement . a5 op39 output high speed output. a6 on37 output high speed output complement . a7 op37 output high speed output. a8 on35 output high speed output complement . a9 op35 output high speed output . a10 on33 output high speed output comple ment . a11 op33 output high speed output. a12 on31 output high speed output complement . a13 op31 output high speed output . a14 on29 output high speed output complement . a15 op29 output high speed output . a16 on27 output high speed output complement . a17 op27 output high speed output . a18 on25 output high speed output complement . a19 op25 output high speed output . a20 on23 output high speed output complement . a21 op23 output high speed output . a22 on21 output high speed output complement . a23 op2 1 output high speed output . a24 v ee power negative supply . a25 v ee power negative supply . a26 v ee power negative supply . b1 v ee power negative supply . b2 v ee power negative supply . b3 v ee power negative supply. b4 v ee power negative supply. b5 on38 output high speed output complement . b6 op38 output high speed output . b7 on36 output high speed output complement . b8 op36 output high speed output . b9 on34 output high speed output complement . b10 op34 output high speed output . b11 on32 output high speed output complement . b12 op32 output high speed output . b13 on30 output high speed output complement . b14 op30 output high speed output . b15 on28 output high speed output complement . b16 op28 output high speed output . b17 on26 output high speed output complement . b18 op26 output high speed output . b19 on24 output high speed output complement . b20 op24 output high speed output . b21 on22 output high speed output complement . b22 op22 output high speed output . adn4605 data sheet rev. a | page 10 of 56 pin no. mnemonic type description b23 on20 output high spe ed output complement . b24 op20 output high speed output . b25 v ee power negative supply. b26 v ee power negative supply. c1 v ee power negative supply. c2 ip0 input high speed input . c3 v ee power negative supply. c4 v cc power positive supply . c5 v cc power positive supply . c6 v cc power positive supply . c7 v ttob power outp ut termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c8 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c9 v ttob power output termination supply (b). t the v ttob pins are normally tied to the v ttoa pins. c10 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c11 v cc power positive supply . c12 v cc power positive sup ply . c13 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c14 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c15 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c16 v cc power positive supply . c17 v cc power positive supply . c18 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c19 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c20 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c21 v ttob power output termination supply (b). the v ttob pins are normally tied to the v ttoa pins. c22 v cc power positive supply . c23 v cc power positive supply . c24 d v cc power digital positive supply . c25 v ee power negative supply. c26 v ee power negative supply. d1 ip1 input high speed input . d2 in0 input high speed input complement . d3 v cc pow er positive supply . d4 d v cc power digital positive supply . d5 v cc power positive supply . d6 v cc power positive supply . d7 v ee power negative supply. d8 v ee power negative supply. d9 v ee power negative supply. d10 v ee power negative supply. d11 v cc power positive supply . d12 v cc power positive supply . data sheet adn4605 rev. a | page 11 of 56 pin no. mnemonic type description d13 v ee power negative supply. d14 v ee power negative supply. d15 v ee power negative supply. d16 v cc power positive supply. d17 v cc power positive supply. d18 v ee power negative supply. d19 v ee power negative supply. d20 v ee power negative supply. d21 v ee power negative supply. d22 v cc power positive supply. d23 d v cc power digital positive supply. d24 v cc power positive supply. d25 v ee power negative supply. d26 in39 input high speed input complement. e1 in1 input high speed input complement. e2 ip2 input high speed input . e3 v cc power positive supply. e4 v ee power negative supply. e23 v ee power negative supply. e24 v cc power positive supply. e25 in38 input high speed input complemen t. e26 ip39 input high speed input f1 ip3 input high speed input f2 in2 input high speed input complement. f3 v ttia power input termination supply (a). the v ttia pins are normally tied to the v ttib pins. f4 v ee power negative supply. f23 v ee power n egative supply. f24 v ttib power input termination supply (b). the v tti b pins are normally tied to the v ttia pins. f25 ip38 input high speed input . f26 in37 input high speed input complement. g1 in3 input high speed input complement. g2 ip4 input high speed input . g3 v ttia power input termination supply (a). the v ttia pins are normally tied to the v ttib pins. g4 v ee power negative supply. g23 v ee power negative supply. g24 v ttib power input terminatio n supply (b). the v ttib pins are normally tied to the v ttia pins. g25 in36 input high speed input complement. g26 ip37 input high speed input . h1 ip5 input high speed input . h2 in4 input high speed input complement. h3 v ttia power input termination supply (a). the v ttia pins are normally tied to the v ttib pins. h4 v ee power negative supply. h23 we /scl/ sck control parallel control interface: first - rank write strobe ( we ) active l ow. i 2 c control interface : i 2 c clock (scl) . spi control interface : spi clock (s ck). h24 v ttib power input termination supply (b). the v tti b pins are normally tied to the v ttia pins. adn4605 data sheet rev. a | page 12 of 56 pin no. mnemonic type description h25 ip36 input high speed input . h26 in35 input high speed input complement. j1 in5 input high speed input complement. j2 ip6 input high speed inp ut. j3 v ttia power inp ut termination supply (a). the v ttia pins are normally tied to the v ttib pins. j4 i 2 c/ spi / update control i 2 c control interface selection (i 2 c). spi control interface selection ( spi ) a ctive l ow. parallel control interface ( update ) active l ow . j23 re / sdi control parallel control interface: read strobe ( re ) active low. spi control in terface : data input (sdi) spi c ontrol . j24 v ttib power input termination supply (b). the v tti b pins are normally tied to the v ttia pins. j25 in 34 input high speed input . j26 i p35 input high speed input complement. k1 ip7 input high speed input . k2 in6 input high speed input complement. k 3 v cc power power supply. k4 ser/ par control ser ial control interface selection (ser). parallel control interface selection ( par ) active l ow. k23 cs control chip select active low . k24 v cc power p ositive supply. k25 ip34 input high speed input . k26 in33 input high speed input complement. l1 in7 input high speed input complement. l2 ip8 input high speed input . l3 v cc power positive supply. l4 reset control configuration r egisters: reset (active low). this pin is normally pulled up to dv cc . l23 data0 / sda /sdo control parallel control interface: register data bit 0 (data0). i 2 c control interface: data in (sda). spi control interface: data out (sdo). l24 v cc power positive s upply. l25 in32 input high speed input complement. l26 ip33 input high speed input . m1 ip9 input high speed input . m2 in8 input high speed input complement. m3 v ttia power input termination supply (a). the v ttia pins are normally tied to the v ttib pi ns. m4 addr0 control parallel control interface: register address bit 0. i 2 c control interface: slave address bit 0 . m23 data1 / update control parallel control interface: register (data1). data bit 1. i 2 c or spi serial control interfac e ( update ). active l ow. m24 v ttib power input termination supply (b). the v tt ib pins are normally tied to the v ttia pins. m25 ip32 input high speed input m26 in31 input high speed input complement. n1 in9 input high speed input com plement. n2 ip10 input high speed input . n3 v ttia power input termination supply (a). the v ttia pins are normally tied to the v ttib pins. n4 addr1 control parallel control interface: register address bit 1. i 2 c control interface: slave address bit 1 . data sheet adn4605 rev. a | page 13 of 56 pin no. mnemonic type description n23 data2 control parallel control interface: register data bit 2 . n24 v ttib power input termination supply (b). the v tti b pins are normally tied to the v ttia pins. n25 in30 input high speed input complement. n26 ip31 input high speed input . p1 ip11 i nput high speed input . p2 in10 input high speed input complement. p3 v ttia power input termination supply (a). the v tt ia pins are normally tied to the v ttib pins. p4 addr2 control parallel control interface: register address bit 2. i 2 c control interfac e: slave address bit 2 . p23 data3 control parallel control interface: register data bit 3 . p24 v ttib power input termination supply (b). the v tti b pins are normally tied to the v ttia pins. p25 ip30 input high speed input . p26 in29 input high speed inp ut complement. r1 in11 input high speed input complement. r2 ip12 input high speed input . r3 v cc power po sitive supply. r4 addr3 control parallel control interface: register address bit 3. i 2 c control interface: slave address bit 3 . r23 data4 control parallel control interface: register data bit 4. r24 v cc power positive supply . r25 in28 input high speed input complement. r26 ip29 input high speed input . t1 ip13 input high speed input . t2 in12 input high speed input complement. t3 v cc power posit ive supply. t4 addr4 control parallel control interface: register address bit 4. i 2 c control interface: slave address bit 4 . t23 data5 control parallel control interface: register data bit 5. t24 v cc power positive supply. t25 ip28 input high speed inp ut . t26 in27 input high speed input complement. u1 in13 input high speed input complement. u2 ip14 input high speed input . u3 v ttia power input termination supply (a). the v ttia pins are normally tied to the v ttib pins. u4 addr5 control parallel cont rol interface: register address bit 5. i 2 c control interface: slave address bit 5 . u23 data6 control parallel control interface: register data bit 6. u24 v ttib power input termination supply (b). the v tti b pins are normally tied to the v ttia pins. u25 in26 input high speed input complement. u26 ip27 input high speed input . v1 ip15 input high speed input . v2 in14 input high speed input complement. v3 v ttia power input termination supply (a). the v ttia pins are normally tied to the v ttib pins. v4 ad dr6 control parallel control interface: register address bit 6. i 2 c control interface: slave address bit 6 . v23 data7 control parallel control interface: register data bit 7. adn4605 data sheet rev. a | page 14 of 5 6 pin no. mnemonic type description v24 v ttib power input termination supply (b). the v tti b pins are normally tied to the v ttia pins. v25 ip26 input high speed input . v26 in25 input high speed input complement. w1 in15 input high speed input complement. w2 ip16 input high speed input . w3 v ttia power input termination supply (a). the v ttia pins are normally tied t o the v ttib pins. w4 addr7 control parallel control interface: register address bit 7. i 2 c control interface: slave address bit 7 . w23 v ee power negative supply. w24 v ttib power input termination supply (b). the v ttib pins are normally tied to the v t tia pins. w25 in24 input high speed input complement. w26 ip25 input high speed input . y1 ip17 input high speed input . y2 in16 input high speed input complement. y3 v ttia power inp ut termination supply (a). the v ttia pins are normally tied to the v tt ib pins. y4 v ee power negative supply. y23 v ee power negative supply. y24 v ttib power input termination supply (b). the v ttob pins are normally tied to the v ttia pins. y25 ip24 input high speed input . y26 in23 input high speed input complement. aa1 in17 input high speed input complement. aa2 ip18 input high speed input . aa3 v cc power po sitive supply. aa4 v ee power negative supply. aa23 v ee power negative supply. aa24 v cc power positive supply. aa25 in22 input high speed input complement. aa26 ip23 input high speed input . ab1 ip19 input high speed input . ab2 in18 input high speed input complement. ab3 v cc power positive supply. ab4 v ee power negative supply. ab23 v ee power negative supply. ab24 v cc power positive supply. ab25 ip22 input h igh speed input . ab26 in21 input high speed input complement. ac1 in19 input high speed input complement. ac2 v ee power negative supply. ac3 v cc power positive supply. ac4 d v cc power digital po sitive supply. ac5 v cc power positive supply. ac6 v cc po wer positive supply. ac7 v ee power negative supply. ac8 v ee power negative supply. ac9 v ee power negative supply. ac10 v ee power negative supply. data sheet adn4605 rev. a | page 15 of 56 pin no. mnemonic type description ac11 v cc power positive supply. ac12 v cc power positive supply. ac13 v ee power negative supply. ac14 v ee power negative supply. ac15 v ee power negative supply. ac16 v cc power positive supply. ac17 v cc power positive supply. ac18 v ee power negative supply. ac19 v ee power negative supply. ac20 v ee power negative supply. ac21 v ee power negative supply. ac22 v cc power positive supply. ac23 d v cc power digital po sitive supply. ac24 v cc power positive supply. ac25 in20 input high speed input complement. ac26 ip21 input high speed input . ad1 v ee power negative supply. ad2 v ee power negative supply. a d3 v ee power negative supply. ad4 v cc power positive supply. ad5 v cc power positive supply. ad6 v cc power positive supply. ad7 v ttoa power outp ut termination supply (a). the v ttoa pins are normally tied to the v ttob pins. ad8 v ttoa power output termin ation supply (a). the v ttoa pins are normally tied to the v ttob pins. ad9 v ttoa power output termination supply (a). the v ttoa pins are normally tied to the v ttob pins. ad10 v ttoa power output termination supply (a). the v ttoa pins are normally tied to t he v ttob pins. ad11 v cc power positive supply. ad12 v cc power positive supply. ad13 v ttoa power output termination supply (a). the v ttoa pins are normally tied to the v ttob pins. ad14 v ttoa power output termination supply (a). the v ttoa pins are normal ly tied to the v ttob pins. ad15 v ttoa power output termination supply (a). the v ttoa pins are normally tied to the v ttob pins. ad16 v cc power positive supply. ad17 v cc power positive supply. ad18 v ttoa power output termination supply (a). the v ttoa pin s are normally tied to the v ttob pins. ad19 v ttoa power out put termination supply (a). the v ttoa pins are normally tied to the v ttob pins. ad20 v ttoa power output termination supply (a). the v ttoa pins are normally tied to the v ttob pins. ad21 v ttoa pow er output termination supply (a). the v ttoa pins are normally tied to the v ttob pins. ad22 v cc power positive supply. ad23 v cc power positive supply. ad24 v ee power negative supply. ad25 ip20 input high speed input . ad26 v ee power negative supply. adn4605 data sheet rev. a | page 16 of 56 pin no. mnemonic type description ae1 v ee power negative supply. ae2 v ee power negative supply. ae3 op0 output high speed output . ae4 on0 output high speed output complement . ae5 op2 output high speed output . ae6 on2 output high speed output complement . ae7 op4 output high speed output . ae8 on4 output high speed output complement . ae9 op6 output high speed output . ae10 on6 output high speed output complement . ae11 op8 output high speed output . ae12 on8 output high speed output complement . ae13 op10 output high speed output . ae14 on10 output high speed output complement . ae15 op12 output high speed output . ae16 on12 output high speed output complement . ae17 op14 output high speed output . ae18 on14 output high speed output complement . ae19 op16 output high speed output . ae20 o n16 output high speed output complement . ae21 op18 output high speed output . ae22 on18 output high speed output complement . ae23 v ee power negative supply. ae24 v ee power negative supply. ae25 v ee power negative supply. ae26 v ee power negative supply . af1 v ee power negative supply. af2 v ee power negative supply. af3 v ee power negative supply. af4 op1 output high speed output . af5 on1 output high speed output complement . af6 op3 output high speed output . af7 on3 output high speed output compleme nt . af8 op5 output high speed output . af9 on5 output high speed output complement . af10 op7 output high speed output . af11 on7 output high speed output complement . af12 op9 output high speed output . af13 on9 output high speed output complement . af14 op11 output high speed output . af15 on11 output high speed output complement . af16 op13 output high speed output . af17 on13 output high speed output complement . af18 op15 output high speed output . af19 on15 output high speed output complement . af20 op17 output high speed output . af21 on17 output high speed output complement . af22 op19 output high speed output. data sheet adn4605 rev. a | page 17 of 56 pin no. mnemonic type description af23 on19 output high speed output complement . af24 v ee power negative supply. af25 v ee power negative supply. af26 v ee power negative s upply. adn4605 data sheet rev. a | page 18 of 56 typical performance characteristics v cc = 2.5 v, v tti x = 2.5 v, v tto x = 2.5 v, dv cc = 3.3 v, v ee = 0 v, r l = 50 ? , output level (olev) = 4 (16 ma), preemphasis (pe) = 0 (0 db), equalizer (eq) = 1 (3 db), data rate = 4.25 gbps (prbs7 data patter n), ac - coupled inputs and outputs, differential input swing = 800 mv p - p, t a = 25 c, unless otherwise noted. 50? cables 2 2 high speed sampling oscilloscope 50? cables 2 2 50? adn4605 ac-coupled ev alu a tion board input pin output pin pa ttern gener a t or dat a out tp2 tp1 09796-048 figure 7 . standard test circuit 09796-035 0.167ui/div 200mv/div figure 8 . 3.25 gbps input eye (tp1 from figure 7 ) 09796-047 0.167ui/div 200mv/div figure 9 . 4.25 gbps input eye (tp1 from figure 7 ) 09796-034 0.167ui/div 200mv/div figure 10 . 3.25 gbps output eye (tp2 from figure 7 ) 09796-046 0.167ui/div 200mv/div figure 11 . 4.25 gbps output eye (tp2 from figure 7 ) data sheet adn4605 rev. a | page 19 of 56 50? cables 2 2 tp3 high speed sampling oscilloscope 50? cables 2 2 50? adn4605 ac-coupled evaluation board input pin output pin pattern generator data out tp1 50? cables 2 2 tp2 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height lengths = 10 inches, 20 inches, 30 inches, 40 inches 09796-049 figure 12 . equalization test circuit 09796-040 0.167ui/div 200mv/div figure 13 . 4.25 gbps input eye, 20 inch fr4 input channel (tp2 from figure 12 ) 09796-045 0.167ui/div 200mv/div figure 14 . 4.25 gbps input eye, 40 - inch fr4 input channel (tp2 from figure 12) 09796-038 0.167ui/div 200mv/div figure 15 . 4.25 gbps output eye, 20 - inch fr4 input channel, eq = 12 db (tp3 from figure 12) 09796-043 0.167ui/div 200mv/div figure 16 . 4.25 gbps output eye, 40 - inch fr4 input channel, eq = 12 db (tp3 from figure 12) adn4605 data sheet rev. a | page 20 of 56 50? cables 2 2 tp3 high speed sampling oscilloscope 50? cables 2 2 50? adn4605 ac-coupled evaluation board input pin output pin pattern generator data out tp1 50? cables 2 2 tp2 fr4 test backplane differential stripline traces 8mils wide, 8mils space, 8mils dielectric height lengths = 10 inches, 20 inches, 30 inches, 40 inches 09796-050 figure 17 . preemphasis test circuit 09796-039 0.167ui/div 200mv/div figure 18 . 4.25 gbps output eye, 20 - inch fr4 output channel, pe = 0 db (tp3 from figure 17) 09796-044 0.167ui/div 200mv/div figure 19 . 4.25 gbps output eye, 40 - inch fr4 input channel , pe = 0 db (tp3 from figure 17) 09796-036 0.167ui/div 200mv/div figure 20 . 4.25 gbps output eye, 20 - inch fr4 input channel , pe = 5.6 db (t p3 from figure 17) 09796-041 0.167ui/div 200mv/div figure 21 . 4.25 gbps output eye, 40 - inch fr4 input channel , pe = 9.5 db (tp3 from figure 17) data sheet adn4605 rev. a | page 21 of 56 0 20 40 60 80 100 0 1 2 3 4 5 deterministic jitter (ps) dat a r a te (gbps) 09796-033 eq = 3db eq = 6db eq = 12db figure 22 . deterministic jitter vs. data rate 0 20 40 60 80 100 2.25 2.50 2.75 3.00 3.25 3.50 3.75 deterministic jitter (ps) supp l y vo lt age (v) 09796-024 eq = 3db eq = 6db eq = 12db figure 23 . deterministic jitter vs. supply voltage 0 20 40 60 80 100 ?40 ?15 10 35 60 85 deterministic jitter (ps) temper a ture (c) 09796-025 eq = 3db eq = 6db eq = 12db figure 24 . deterministic jitter vs. temperature 0 100 200 300 400 500 600 700 800 900 1000 0 1 2 3 4 5 eye height (mv p-p diff ) dat a r a te (gbps) 09796-030 figure 25 . eye height vs. data rate 0 100 200 300 400 500 600 700 800 900 1000 2.25 2.50 2.75 3.00 3.25 3.50 3.75 eye height (mv p-p diff ) supp l y vo lt age (v) 09796-027 figure 26 . eye height vs. supply voltage 0 100 200 300 400 500 600 700 800 900 1000 ?40 ?15 10 35 60 85 temper a ture (c) eye height (mv p-p diff ) eq = 3db eq = 6db eq = 12db 09796-026 figure 27 . eye height vs. temperature adn4605 data sheet rev. a | page 22 of 56 0 10 20 30 40 50 60 0 10 20 30 40 deterministic jitter (ps) input fr4 trace length (inches) 09796-032 eq = 3db eq = 6db eq = 12db figure 28 . deterministic jitter vs. input fr4 channel length 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 jitter (ps) input swing (v diff p-p ) deterministic jitter p-p random jitter rms 09796-029 figure 29 . jitter vs. differential input swing 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 deterministic jitter (ps) termin a tion vo lt age (v) v cc = 2.5v v cc = 3.3v 09796-022 figure 30 . deterministic jitter vs. output termination voltage (v tto ) 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 deterministic jitter (ps) output fr4 channe l length (inches) 09796-031 0db 2.2db 3.5db 5.4db 6.0db 7.4db 9.5db figure 31 . deterministic jitter vs. output fr4 channel length 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 jitter (ps) input common-mode (v) random jitter rms deterministic jitter p-p 09796-028 figure 32 . jitter vs. input common - mode voltage ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 100k 1m 10m 100m 1g 10g 09796-017 loss (db) frequenc y (hz) 6 inches 10 inches 20 inches 40 inches 30 inches figure 33 . s21 test traces data sheet adn4605 rev. a | page 23 of 56 0 20 40 60 80 100 120 140 ?40 ?20 0 20 40 60 80 100 rise/ f al l time (ps) temper a ture (c) rise time fall time 09796-018 figure 34 . rise/fall time vs. temperature 800 850 900 950 1000 1050 1 100 1 150 1200 2.375 2.500 3.300 3.630 pro p ag a tion del a y (ps) supp l y vo lt age (v) 09796-051 figure 35 . propagatio n delay vs. supply voltage 160 152 144 136 128 120 1 12 104 96 88 80 72 64 56 48 40 32 24 16 8 0 samples pro p ag a tion del a y (ps) 700 720 740 760 780 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1 100 prop delay mean 922.4ps 09796-023 figure 36 . propagation delay histogram 09796-021 0 5000 10000 15000 20000 25000 ?4.0 ?3.7 ?3.4 ?3.0 ?2.7 ?2.4 ?2.1 ?1.8 ?1.4 ?1.1 ?0.8 ?0.5 ?0.2 0.2 0.5 0.8 1.1 1.4 1.8 2.1 2.4 2.7 3.0 3.4 3.7 4.0 samples random jitter (ps) standard deviation = 0.81ps figure 37 . random jitter histogram 800 850 900 950 1000 1050 1 100 1 150 1200 ?40 ?20 0 20 40 60 80 100 pro p ag a tion del a y (ps) temper a tur e (c) v cc = 2.5v v cc = 3.3v 09796-020 figure 38 . propagation delay vs. temperature ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10m 100m 1g 10g return loss (db) frequenc y (hz) s 22 s 11 09796-019 figure 39 . return loss (s11, s22 ) adn4605 data sheet rev. a | page 24 of 56 theory of operation introduction the adn4605 is a 40 40 , buffered, asynchronous crosspoint switch that provides input equalization, output preemphasis , and output level programming capabilities . the receivers integrate an equalizer that is optimized to compensate for typical backplane losses. the switch supports multicast and broadcast operation, allowing the adn460 5 to work in redundancy and port replication applic ations. the adn4605 is configured through either the serial or parallel control interface. the serial or parallel control interface is selected using the ser/ par dedicated control pin. the serial interface supports both i 2 c and spi protocols selected using the i 2 c/ spi dedicated control pin. the adn4605 control pins function differently depending on which programming interface is selected , as described in table 8 . eq rx tx pre- emphasis 40 40 switch ma trix connection ma p 1 connection ma p 0 p arallel/seria l contro l logic inter f ace pre- emphasis leve l settings output leve l settings adn4605 v cc v ee dv cc op[39:0] v tt oa , v tt ob on[39:0] ip[39:0] v tti a , v ttib in[39:0] i 2 c/spi (upd a te) sdi/re scl/sck/ we reset ser/ p ar cs equaliz a tion settings dat a[1] (upd a te) dat a[0]/ sda/sdo dat a[7:2] addr[7:0] 09796-007 figure 40 . block diagram table 8. parallel/ serial interface pin control pin no. pin name parallel mode (ser/ par = 0) i 2 c mode (ser/ par = 1, i 2 c / spi = 1) spi mode (ser/ par = 1, i 2 c / spi = 0) pin function pin function pin function k4 ser/ par serial/parallel control interface se lection serial/parallel control interface selection serial/parallel control interface selection j4 i 2 c/ spi / update upda te s t robe i 2 c/ spi control interface selection i 2 c/ spi control interface selection h23 we /scl/sck parallel write strobe i 2 c c lock spi c lock j23 re /sdi parallel read strobe n/a spi data input k23 cs chip select n/a chip select l23 data 0 /sda/sdo parallel regi ster data bit (lsb) i 2 c data input spi data output m23 data1/ update parallel register data bits update s trobe update s trobe n23, p23, r23, t23, u23, v23 data2 to data7 parallel register data bits n/a n/a l4 reset d evice register reset (active low) device register reset (active low) device register reset (active low) m4 addr 0 parallel register address bit (lsb) n/a n/a n4, p4, r4, t4, u4, v4, w4 addr1to addr7 parallel register address bits i 2 c lsb device address t o i 2 c m sb device address n/a data sheet adn4605 rev. a | page 25 of 56 receivers input structure and input levels the adn4605 receiver inputs incorporate 50 termination resistors, esd protection, and a fixed equalizer that is optimized for operation over long backplane traces. each receive channel also provides a positive/negative (p/n) inversion function, which allows the us er to swap the sign of the input signal path to eliminate the need for board - level crossovers. equalization the adn4605 receiver incorporates a continuous time equalizer (eq) that provides up to 12 db of high frequency boost to com - pensate up to 40 inches of fr4 at 4.25 gbps. each input has two equalizer control bit s . the receiver is disabled by default. the boost can be set to defined levels by prog ramming the respective address register bit s (address 0xc0 thr ough address 0xc9) for the target input channel to the specified logic combinations as shown in table 9 . v cc v tti ipx inx v ee r2 210? r4 630? rn 53 ? rp 53 ? r1 210? r3 630? 600 a 600 a equalizer 09796-008 figure 41 . simplified input circuit table 9. equali zation control registers register address default register name bits bit name functionality description 0xc0 0x0 r x eq control (rx in 3 to r x in 0 ) 7:6 rxeqin [ 3 ] 00 = rx disabled (default) 01 = 3 db boost 10 = 6 db boost 11 = 12 db boost 5:4 rxeqin [ 2 ] 3:2 rxeqin [ 1 ] 1:0 rxeqin [ 0 ] 0xc1 0x0 r x eq control ( r x in 7 to r x in 4 ) 7:6 rxeqin [ 7 ] 5:4 rxeqin [ 6 ] 3:2 rxeqin [ 5 ] 1:0 rxeqin [ 4 ] 0xc2 0x0 r x eq control ( r x in 11 to r x in 8 ) 7:6 rxeqin [ 11] 5:4 rxeqin [ 10] 3 :2 rxeqin [ 9 ] 1:0 rxeqin [ 8 ] 0xc3 0x0 r x eq control ( r x in 15 to r x in 12 ) 7:6 rxeqin [ 15] 5:4 rxeqin [ 14] 3:2 rxeqin [ 13] 1:0 rxeqin [ 12] 0xc4 0x0 r x eq control ( r x in 19 to r x in 16 ) 7:6 rxeqin [ 19] 5:4 rxeqin [ 18] 3:2 r xeqin [ 17] 1:0 rxeqin [ 16] 0xc5 0x0 r x eq control ( r x in 23to r x in 20 ) 7:6 rxeqin [ 23] 5:4 rxeqin [ 22] 3:2 rxeqin [ 21] 1:0 rxeqin [ 20] 0xc6 0x0 r x eq control ( r x in 27 to r x in 24 ) 7:6 rxeqin [ 27] 5:4 rxeqin [ 26] 3:2 rxeq in [ 25] 1:0 rxeqin [ 24] adn4605 data sheet rev. a | page 26 of 56 register address default register name bits bit name functionality description 0xc7 0x0 r x eq control ( r x in 31 to r x in 28 ) 7:6 rxeqin [ 31] 00 = rx disabled (default) 01 = 3 db boost 10 = 6 db boost 11 = 12 db boost 5:4 rxeqin [ 30] 3:2 rxeqin [ 29] 1:0 rxeqin [ 28] 0xc8 0x0 r x eq contro l ( r x in35 to r x in 32 ) 7:6 rxeqin [ 35] 5:4 rxeqin [ 34] 3:2 rxeqin [ 33] 1:0 rxeqin [ 32] 0xc9 0x0 r x eq control ( r x in 39 to r x in 36 ) 7:6 rxeqin [ 39] 5:4 rxeqin [ 38] 3:2 rxeqin [ 37] 1:0 rxeqin [ 36] 0xca 0x0 (write o nly) r x eq control ( r x in broadcast ) 1:0 rxeqin bc polarity inversion the p/n inversion is a feature intended to allow the user to implement the equivalent of a board - level crossover in a much smaller area and without additional via impedance discontinuities t hat degrade the high frequency integrity of the signal path. the p/n inversion is available independently for each of the 40 input and output channels, which are controlled by writing to the rxsign bit of the rx sign control registers (addresses 0xcb throu gh address 0xcf) and the txsign bit of the tx control registers (address 0xa9 through address 0xad). table 10. signal path polarity control register addr ess default register name bit s bit name functionality description 0xcb 0x00 rx sign rx in 07 to rx in 00 7: 0 rxsign [ 7 ] to rxsign [ 0 ] signal path polarity inversion ( input/output) 0 = n oni nvert 1 = i nvert 0xcc 0x00 rx sign rx in 15 to rx in 08 7: 0 rxsign [ 15] to rxsign [ 8 ] 0xcd 0x00 rx sign rx in 23 to rx in 16 7: 0 rxsign [ 23] to rxsign [ 16] 0xce 0x00 rx sign rx in31 to rx in 24 7: 0 rxsign [ 31] to rxsign [ 24] 0xcf 0x00 rx sign rx in 39 to rx in 32 7: 0 rxsign [ 39] to rxsign [ 32] 0xa9 0x00 tx sign tx out 07 to tx out 00 7: 0 txsign [ 7 ] to txsign [ 0 ] 0xaa 0x00 tx sign tx out 15 to tx out 08 7: 0 txsign [ 1 5 ] to txsign [ 8 ] 0xab 0x00 tx sign tx out 23 to tx out 16 7: 0 txsign [ 23] to txsign [ 16] 0xac 0x00 tx sign tx out 31 to tx out 24 7: 0 txsign [ 31] to txsign [ 24] 0xad 0x00 tx sign tx out 39 to tx out 32 7: 0 txsign [ 39] to txsign [ 32] data sheet adn4605 rev. a | page 27 of 56 switch core the adn4605 switch core is a fully non blocking 40 40 array that allows multicast and broadcast configurations. the config - uration of the switch core is progr ammed through either the serial or parallel control interface. the crosspoint configuration map , which controls the connectivity of the switch core , consists of a double rank register architect ure , as shown in figur e 42. the second rank registers contain the current state of the cross point. the first rank registers contain the next state. each entry in the connection map stores six bits per output, which indicates which of the 40 inputs are connected to a given out put. an entire connectivity matrix can be programmed at once by passing data from the first rank registers into the second rank by writing 0x01 to the xpt u pdate r egister (address 0x01). an external update pin can also be used to contro l the data transfer as shown in table 8 . the first rank registers store connecti on configurations for the cross point. map 0 is the defa ult map and is located at address 0x04 to address 0x2b. by default, map 0 cont ains a diagonal co nnection configuration whereby i nput 0 is connected to output 0 , i nput 1 to o utput 1 , i nput 2 to o utput 2 , and so on. similarly, by default, map 1 contains the opposite diagonal connection configuration where i nput 0 is connected to o utput 39, i nput 1 to o utput 38, and so on. both maps are read/write accessible registers. the active map is selected by writing to the xpt map table s elect register (address 0x02). the crosspoint is configured by addressing the register assigned to the des ired output and writing the desired connection data into the first rank of latches in either map 0 or map 1. the connection data is equivalent to the binary coded value of the input number. this process is repeated until each of the desired connections is programmed. in situations where multiple o utputs are to be programmed to a single input, a broadcast command is available. a broadcast command is issued by writing the binary value o f the desired input to the xpt b roadcast register ( address 0x03). the br oad - cast is applied to the selected map table . the current state of the crosspoint connectivity is available by reading the xpt s tatus registers (address 0x54 to address 0x7b). register descriptions for map 0, map 1 , and xpt status registers are shown in table 11. 0 39 0 39 inputs inputs register 0x04 t o register 0x2b xpt map 0 outputs register 0x2c t o register 0x53 xpt map 1 outputs 0 1 map table select register 0x02 xpt s ta tus read register 0x54 t o register 0x7b update register 0x01/ external pin first rank registers second rank registers 0 39 0 39 xpt core outputs 09796-009 0 39 0 39 inputs figure 42 . crosspoint connection map block diagram adn4605 data sheet rev. a | page 28 of 56 table 11. xpt control registers register address default register name bits bit name function ality description 0x00 0x00 (write only) software reset 0 software reset reset the adn4605 registers to default values 0x01 0x00 (write only) xpt update 0 xpt update updates xpt switch core (active high) 0x02 0x00 xpt map table select 0 map table select 0: map 0 is selected (default) 1: map 1 is selected 0x03 0x00 (write only) xpt broadcast 5:0 xpt bcast [5:0] a ssigns all output values at once for the selected xpt table map 0x04 to 0x2b 0x00 to 0x27 xpt map 0 control 0 to control 39 5:0 out x [5:0] output (x = 0 to 39) connection assignments 0x2c to 0x53 0x27 to 0x00 xpt map 1 control 39 to control 0 5:0 out x [5:0] output (x = 39 to 0) connection assignments 0x54 to 0x7b 0x00 to 0x00 xpt status control 39 to control 0 5:0 out x [5:0] output (x = 0 to 39) connection status reset on initial power-up, or at any point in operation, the adn4605 register set can be restored to the default values by pulling the reset pin low according to the control logic timing specifications. during normal operation, however, the reset pin must be pulled up to dv cc . a software reset is also available by writing the value 0x01 to the reset register at address 0x00. this register is write-only. data sheet adn4605 rev. a | page 29 of 56 transmitters output structure and out put levels the adn4605 transmitter outputs incorporate 50 ? termin - ation resistors, esd protection, and output current switches. each channel provides independent control of both the absolute output level and the preemphasis output level. note that the choice of output current affects the output common - mode level. preemphasis transmission line attenuation can be equalized at the trans - mitter using preemphasis. the transmit equalizer setting can be chosen by matching the channel loss to the amount of boost provided by the preem phasis. transmitter preemphasis levels, as well as dc output levels, can be set through either the serial or parallel control interface. table 12 summa rizes the absolute output level s and preemphasis level control setting s. the output level control sets the dc current level , and the preemphasis level control sets the pe current in the transmitter, as shown in figure 43. the full resolution of eight settings is available through the serial or parallel interface. a single setting can be programmed to all outputs simulta neously by writing to the tx lane cont rol broadcast register (address 0xa8 ) . in addition to the enable d state , t he t x has three possible disabled states ( standby, squelched, and dis abled) controlled by the t x drive control registers ( address 0xb0 to address 0xb9) shown in table 13 . disabled is the lowest power - down state. when squelched, the output voltage at both the p and n outputs is the common - mode voltage as defined by the output current settings. note that the squelch feature is only available when using a 3.3 v core supply voltage (v cc ) . in standby, the output level of both p and n outputs is pulled up to the termination supply ( v tto a or v tto b ). on-chi p termin a tion esd v cc v ttox opx onx v ee v3 vc v2 vp v1 vn q1 i dc + i pe = i t q2 rp 50? rn 50? 09796-010 figure 43 . simplified t x output circuit table 12. preemphasis and output level settings register address default register name bits bit name description 0x80 (output 0) to 0xa7 (outpu t 39) and 0xa8 (t x broadcast) 0x40 tx lane control output 0 to tx lane control output 39 and tx broadcast 7 reserved 0 ( reserve b it) 6:4 olev 000: 0 ma 001: 4 ma 010: 8 ma 011: 12 ma 100: 16 ma 101: 20 ma 110: 24 ma 111: (reserve bit) 3 overdrive 1: overdrive (increases olev and pe currents by 25%) 0: n o overdrive 2:0 pe 000: 0 ma 001: 2 ma 010: 3 ma 011: 4 ma 100: 5 ma 101: 6 ma 110: 7 ma 111: 8 ma adn4605 data sheet rev. a | page 30 of 56 table 13. transmitter output enable state settings register address default register name bits bit name functionality description 0xb0 0x00 tx drive control tx3 to tx0 7:6 5:4 3:2 1:0 tx en [ 3 ] txen [ 2 ] txen [ 1 ] txen [ 0 ] 11: e nabled 10: t x s tandby 01: t x s quelched 00: t x d isabled (default) 0xb1 0x00 tx drive control tx7 to tx4 7:6 5:4 3:2 1:0 txen [ 7 ] txen [ 6 ] txen [ 5 ] txen [ 4 ] 0xb2 0x00 tx drive control tx11 to tx8 7:6 5:4 3:2 1:0 txen [ 11 ] txen [ 10 ] txen [ 9 ] txen [ 8 ] 0xb3 0x00 tx drive control tx15 to tx12 7:6 5:4 3:2 1:0 txen [ 15 ] txen [ 14 ] txen [ 13 ] txen [ 12 ] 0xb4 0x00 tx drive control tx19 to tx16 7:6 5:4 3:2 1:0 txen [ 19 ] txen [ 18 ] txen [ 17 ] txen [ 16 ] 0xb5 0x00 tx drive control tx23 to tx20 7:6 5:4 3:2 1:0 txen [ 23 ] txe n [ 22 ] txen [ 21 ] txen [ 20 ] 0xb6 0x00 tx drive control tx27 to tx24 7:6 5:4 3:2 1:0 txen [ 27 ] txen [ 26 ] txen [ 25 ] txen [ 24 ] 0xb7 0x00 tx drive control tx31 to tx28 7:6 5:4 3:2 1:0 txen [ 31 ] txen [ 30 ] txen [ 29 ] txen [ 28 ] 0xb8 0x00 drive control tx35 to tx32 7:6 5:4 3:2 1:0 txen [ 35 ] txen [ 34 ] txen [ 33 ] txen [ 32 ] 0xb9 0x00 drive control tx39 to tx36 7:6 5:4 3:2 1:0 txen [ 39 ] txen [ 38 ] txen [ 37 ] txen [ 36 ] 0xba 0x00 (write only) t x drive control 1:0 tx en bc [39] data sheet adn4605 rev. a | page 31 of 56 the amount of high frequency boost provided by the transmit - ter is dete rmined by both the output and preemphasis level settings. table 14 provides an example of how the absolute output and preemphasis level settings determine the amount of high fr equency boost at the t x output. note that the olev setting refers to the main tap output current and the pe setting refers to the delayed tap current. the preemphasis boost equation follows: ? ? ? ? ? ? ? ? ? + = ? ? ? v v v dc sw dc sw pe sw gain 1 log 20 ] db [ 10 (1) v tto v h-pe v sw-pe v l-pe v l-dc v sw-dc v h-dc v ocm t pe 09796-0 1 1 figure 44 . signal level definitions table 14 . preemphasis boost and overshoot vs. setting example pe setting delayed tap current (ma) olev setting main tap current (ma) gain (db) overshoot () dc swing (mv p - p diff ) 0 0 4 16 0.00 0.00 800 3 4 5 20 3.52 50.00 800 7 8 6 24 6.02 100.00 800 7 8 4 16 9.54 200.00 400 7 8 3 12 13.98 400.00 200 table 15. symbol definitions symbol formula definition i dc programmable output current for main tap output level (olev) i pe programmable output current for pe delayed tap (pe) i tto i dc + i pe total transmitter output current v d pp- dc 25 ? i dc 2 peak -to - peak d ifferential voltage swing of non preemphasized waveform v dpp - pe 25 ? i tto 2 peak -to - peak differential voltage sw ing of preemphasized waveform v sw - dc v dpp - dc /2 = v h- dc C v l - dc dc s ingle - ended voltage swing v sw - pe v dpp - pe /2 = v h- pe C v l - pe preemphasized single - ended voltage swing ?v ocm_dc - coupled 25 ? i tto /2 output common - mode shift , dc - coupled outputs ?v ocm_ac - coupled 50 ? i tto /2 output common - mode shift , ac - coupled outputs v ocm v tto ? ?v ocm = ( v h- dc + v l - dc )/ 2 output common - mode voltage v h- dc v tto ? ?v ocm + v d pp- dc /2 dc single - ended output high voltage v l - dc v tto ? ?v ocm ? v d pp- dc /2 dc single - ended output low voltage v h- pe v tto ? ?v ocm + v d pp- pe /2 maximum single - ended output voltage v l - pe v tto ? ?v ocm ? v d pp- pe /2 minimum single - ended output voltage adn4605 data sheet rev. a | page 32 of 56 termination the inputs and outputs include integrated 50 termination resistors. the internal resistors can be disabled f or applications that require external termination resistors. for example, disabling the integrated 50 termination resistors allow alternative termination values such as 75 as shown in figure 45 . note that the integrated 50 termination resistors are optimal for high data rate digital signaling. disabling the terminations can r educe the overall performance. the termination control for the receiver inputs can be accessed through register addres s 0xd0 (input 0 to input 19) and register address 0xd1 (input 20 to input 39). the termination control for the transmitter o utputs can be accessed through re gister address 0xbc (output 0 to output 19) and register address 0x bd (output 20 to output 39) . table 16 shows the termination control registers. each bit controls the terminations settings for four inputs/outputs. a logic 0 enables the terminations for the respective group. a logic 1 disables the terminations for the respe ctive group . the terminations are enabled by default. cm l v ee v tt ox v tt ox v cc v ttix adn4605 rx 50? 50? 50? 50? 50? 75? 75? 50? v ttix 75? 75? 50? 50? 09796-012 figure 45 . 75 to 50 impedance translator table 16. termination control register register address default register name bit bit name description functionality 0xbd 0x00 tx termination control 4 3 2 1 0 txb_term txb_term txb_term txb_term txb_term output [39:36] (b side) termination control output [35:32] (b side) termination control output [31:28] (b side) termination control output [27:24] (b si de) termination control output [23:20] (b side) termination control 0 = term ination s enabled 1= t erm ination s disabled 0xbc 0x00 tx termination control 4 3 2 1 0 txa_term txa_term txa_term txa_term txa_term output [19:1 6] (a side) termination control outp ut [15:12] (a side) termination control output [11:8] (a side) termination control output [7:4] (a side) termination control output [3:0] (a side) termination control 0xd1 0x00 rx termination control 4 3 2 1 0 rxb_term rxb_term rxb_term rxb_ter m rxb_term input [39:36] (b side) termination control input [35:32] (b side) termination control input [31:28] (b side) termination control input [27:24] (b side) termination control input [23:20] (b side) termination control 0xd0 0x00 rx termination control 4 3 2 1 0 rxa_term rxa_term rxa_term rxa_term rxa_term input [19:16] (a side) termination control input [15:12] (a side) termination control input [11:8] (a side) termination control input [7:4] (a side) termination control input [3:0] (a side) termination cont rol data sheet adn4605 rev. a | page 33 of 56 i 2 c serial control interface the adn4605 register set is controlled through a 2 - wire i 2 c interface. to a c c e ss the i 2 c serial interface , both the ser/ par line and i 2 c/ spi lines must be held at logic high. the adn4605 acts only as an i 2 c slave device. therefore, the i 2 c bus in the system needs to include an i 2 c master to configure the adn4605 and other i 2 c devices that ma y be on the bus. the adn4605 i 2 c interface can be run in the standard (100 khz) and fast (400 khz) modes. the sda line only changes value when the scl pin is low with two exceptions. to indicate the beginni ng or continuation of a transfer, the sda pin is driven low while the scl pin is high; to indicate the end of a transfer, the sda line is driven high while the scl line is high. therefore, it is important to control the scl clock to toggle only when th e sda line is stable unless indicating a start , repeated start , or stop condition. to establish i 2 c communication with the adn4605 , parallel address lines ( addr[7:1]) ne ed to be configured to the user - assigned i 2 c device address as shown in tabl e 17. table 17. example of i 2 c device address assignment a7 a6 a5 a4 a3 a2 a1 a0 i 2 c device address 1 0 0 1 0 0 0 x 0x90 1 0 0 1 0 0 1 x 0x92 1 0 0 1 0 1 0 x 0x94 1 0 0 1 0 1 1 x 0x96 i 2 c data write to write data to the adn4605 r egister set, a microcontroller, or any other i 2 c master, must send the appropriate control signals to the adn4605 slave device. the steps to be followed are listed below ; the signals are controlled by the i 2 c master unless other - wise specified. a diagram of the procedure is shown in figure 46 . 1. send a start condition (while hol ding the scl line high, pull the sda line low). 2. send the adn4605 part address (seven bits) whose bits are controlled by the input pins addr [ 7 :1 ]. this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the adn4605 to acknowledge the request. 5. send the register address (eight bits) to which data is to be written. this transfer should be msb first. 6. wait for the adn4605 to acknowledge the request. 7. send the data (eight bits) to be written to the register whose address was set in step 5. this transfer should be msb first. 8. wait for the adn4605 to acknowledge the request. 9. do one or more of the following: a. send a stop condition (while holding the scl line high , pull the sda line high) and release control of the bus. b. send a repeated start condition (while holding the scl line high, pull the sda line low) and cont inue with step 2 of the write procedure (see the i 2 c data wr ite section) to perform a write. c. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of this procedure to perform a read from another address. d. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 8 of this procedure to perform a read from the same address. the adn4605 write process is shown in figure 46 . the scl signal is shown along with a general write operation and a specific example. in the example, d ata 0x 4b is written to address 0x6d of an adn460 5 part with a part address of 0x 92. the adn4605 device address selections are more flexible than shown. it is important to note that the sda line only changes when the scl line is low, except for the case of sending a start, stop, or repeated start conditi on, step 1 and step 9 in this case. start r/w ack ack ack stop data addr [1:0] b10010 register addr scl sda sda example 1 2 2 3 4 5 6 7 8 9a 09796-013 figure 46 . i 2 c write diagram adn4605 data sheet rev. a | page 34 of 56 i 2 c data read to read data from the adn4605 register set, a microcontroller, or any other i 2 c master needs to send the appropriate control signals to the adn4605 slave device. the steps are listed below; the signals are controlled by the i 2 c master unless otherwise specified. a diagram of the procedure is shown in figure 47. 1. send a start condition (while holding the scl line high, pull th e sda line low). 2. send the adn4605 part address ( seven bits) whose bits are controlled by the input pins addr[7 :1 ]. this transfer should be msb first . 3. send the write indicator bit (0). 4. wait for the adn4605 to acknowledge the request. 5. send the register addre ss ( eight bits) from which data is to be read. thi s transfer should be msb first. the register address is kept in memory in the adn4605 until the part is reset or the register address is written over with the same procedure ( step 1 to step 6). 6. wa it for t he adn4605 to acknowledge the request. 7. send a repeated start condition (while holding the scl line high, pull the sda line low). 8. send the adn4605 p art address (seven bits) whose bits are controlled by the input pins addr[7 :1 ]. this transfer should be msb f irst . 9. send the read indicator bit (1). 10. wait for the adn4605 to acknowledge the request. 11. the adn4605 then serially transfer s the data (eight bits) held in the register indicated by the address set in s tep 5. 12. acknowledge the data. 13. do one or more of the follo wing: a. send a stop condition (while holding the scl line high pull the sda line high) and release control of the bus. b. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of the write procedure (s ee the i 2 c data wr ite section) to perform a write. c. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 2 of this procedure to perform a read from another address. d. send a repeated start condition (while holding the scl line high, pull the sda line low) and continue with step 8 of this procedure to perform a read from the same address. t he adn4605 read process is shown i n figure 47. the scl signal i s shown along with a general read ope ration and a specific example. in the example, d ata 0x49 is read from a ddress 0x6d of an adn4605 part with a part address of 0x 92 . the part address is seven bits wide and is composed of the adn4605 (addr [7: 1 ]). in this example, the addr {1:0] bits are set to b01. in figure 47 , the corresponding step number is visible in the circle under the waveform. the scl line is driven by the i 2 c master and never by the adn4605 slave. as for the sda line, th e data in the shaded polygons is driven by the adn4605 , whereas t he data in the non shaded polygons is driv en by the i 2 c master. the end phase case shown is that of step 13a. note that the sda line only changes when the scl line is low, except for the case of sending a start , stop , or repeated start condition, as in step 1, step 7, and step 13. in figure 47, a is the same as ack. equally, sr represents a repeated start where the sda line is brought high before scl is raised. sda is then dropped while scl is still high. scl sda sda example 1 2 2 3 4 5 6 7 8 8 9 10 11 12 13a b10010 a a sr data a stop register addr start addr [1:0] addr [1:0] b10010 r/ w a r/ w 09796-014 figure 47 . i 2 c read diagram data sheet adn4605 rev. a | page 35 of 56 spi serial control i nterface the spi serial interface of the adn4605 consists of four wires: cs , sc k, sdi, and sdo. in order to access the spi interface the ser/ par line must be held at logic high and the i 2 c/ spi line must be held at logic low. the cs pin is used to select the device when more than one device is connected to the serial c lock and data lines and must be held at logic low to enable write/read capability to the device when in spi control mode. the sck is used to clock data in and out of the part. the sdi line is used to write to the registers, and the sdo line is used to rea d data back from the registers. data on sdi line is clocked on the rising edge of sck. data on sdo changes on the falling edge of sck. the recommended pull - u p resistor value is between 500 ? and 1 k?. strong pull - ups are needed when serial clock speeds that are close to the maximum limit are used or when the spi interface lines are experiencing large capacitive loading. larger resistor values can be used for pull - up resistors whe n the serial clock speed is reduced. the part operates in a slave mode and requires an externally applied serial clock to the sc k input . the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is sync hronized to the serial data. there are two types of serial operations, a read and a write. command words are used to distinguish between a read and a write operation as shown in table 18. table 18. spi com mand words writ e c ommand 0x02 (0000 0010) read c ommand 0x03 (0000 0011) write operation figure 48 shows the diagram for a write operation to the adn4605 . data is clocked into the registers on the rising ed ge of sc k. when the cs line is high , the sdi and sdo lines are in three - state mode. only when the cs goes from a high to a low does the part a ccept any data on the sdi line. the 8 - bit write command must precede the register address byte. the r egister address byte is then followed by the data byte as shown in figure 48. to allow continuous writes , the address pointer register auto - increment s by one without having to load the address pointer register each time. subsequen t data bytes are written into sequential registers. note that not all registers in the 256 - byte address space exist and not all registers are writable. zeroes should be entered for nonexistent address fields when imple - menting a continuous write operation. address space 0x e0 to address 0xf f is reserved and should not be overwritten . read operation to read back from a register, first send the read command followed by the desired register address. subsequent clock cycles , with cs asserted lo w , stream data starting from the desired register ad dress onto sdo, msb first. sdo changes on the falling edge of sck. multiple data reads are possible in spi interface mode because the address pointer r egister is auto - incremented . adn4605 data sheet rev. a | page 36 of 56 write command start stop register address d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x x x x x x x cs sck sdi sdo data byte x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 cs (continued) sck (continued) sdi (continued) sdo (continued) 1 8 1 8 1 8 09796-015 figure 48 . spi C writing to the address pointer register followed by a single byte of data to the selected register data sheet adn4605 rev. a | page 37 of 56 read command start stop register address d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x x x x x x x cs sck sdi sdo data byte x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 cs (continued) sck (continued) sdi (continued) sdo (continued) 1 8 1 8 1 8 09796-016 figure 49 . sp i C reading a single byte of data from a selected register adn4605 data sheet rev. a | page 38 of 56 parallel control int erface the p aralle l control interface of the adn4605 consists of nineteen wires : addr[7:0], data[7:0], we , re , and cs . t o access the parallel control interface , the ser/ par line must be held at logic low. the cs line is used to select a device when one or more devices share t he same address and data lines. the cs line must be held at logic low to enable write/read c apability to the device when in parallel control mode . address inputs: a ddr [7:0] the binary coded address applied to the address lines determine s which device registers are being programmed or read back. data inputs/outputs: d ata [7:0] in write mode, the b inary encoded data applied to the data lines ( data[7:0] ) determine the configuration setting of the register specified by the address lines ( addr[7:0] ) . in read mode, data lines ( data [ 7:0] ) are low impeda nce outputs indicating the data byte stored in the register specified by t he address line s ( addr[7:0] ) . note that some registers are write only and may not be read from ( see table 19) the read - back drivers are designed to drive high impedances only (>1 k ?). write operation f or first rank write enable, f orcing this pin to logic low allows the data on the data[7:0] lines to be stored in the first rank latch for the register specified by the address lines ( addr[7:0] ) . the data is latched during the high - to - low transition of the write enable pulse. the we line must be returned to a logic high state after the write cycle to avoid overwriting the first rank data. read operation for s econd rank read enable, f orcing this line to a logic low st ate enables the output drivers on the bidir ectional data lines (data[7:0]), placing the logic in readback mode of operation. the register selected to read from is determined by the binary encoded data configured on the address lines (addr[7:0]). when the r ead enable line is at a logic low, the data stored in the specified register will be latched onto the data lines (data[7:0]). the re line is higher priority than the we line; therefore , first rank programming is not p ossible while in readback mode. note that some registers are defined as write only and are not accessible in readback mode ( see tabl e 19). data sheet adn4605 rev. a | page 39 of 56 register map in the register map, when settings are provided in the description column f or the first bit, note that these settings apply to all bits with the same function. table 19 . register map address : channel default register name bit s bit name description 0x00 0x00 software reset 0 reset software reset write o nly 0x01 0x0 xpt u pdate 0 x pt update updates crosspoint switch core write only 0x02 0 x00 xpt map table 0 map table select 0: map 0 is selected select 1: map 1 is selected 0x03 write only xpt b roadcast 5:0 xpt bcast [5:0] all outputs con nection assignment 0x04 0x00 xpt map 0 control 0 5:0 out 0 [5:0] output 0 connection assignment 0x05 0x01 xpt map 0 control 1 5:0 out 1 [5:0] output 1 connection assignment 0x06 0x02 xpt map 0 control 2 5:0 out 2 [5:0] output 2 connection assignment 0x 07 0x03 xpt map 0 control 3 5:0 out 3 [5:0] output 3 connection assignment 0x08 0x04 xpt map 0 control 4 5:0 out 4 [5:0] output 4 connection assignment 0x09 0x05 xpt map 0 control 5 5:0 out 5 [5:0] output 5 connection assignment 0x0a 0x06 xpt map 0 cont rol 6 5:0 out 6 [5:0] output 6 connection assignment 0x0b 0x07 xpt map 0 control 7 5:0 out 7 [5:0] output 7 connection assignment 0x0c 0x08 xpt map 0 control 8 5:0 out 8 [5:0] output 8 connection assignment 0x0d 0x09 xpt map 0 control 9 5:0 out 9 [5:0] output 9 connection assignment 0x0e 0x0a xpt map 0 control 10 5:0 out 10 [5:0] output 10 connection assignment 0x0f 0x0b xpt map 0 control 11 5:0 out 11 [5:0] output 11 connection assignment 0x10 0x0c xpt map 0 control 12 5:0 out 12 [5:0] output 12 conn ection assignment 0x11 0x0d xpt map 0 control 13 5:0 out 13 [5:0] output 13 connection assignment 0x12 0x0e xpt map 0 control 14 5:0 out 14 [5:0] output 14 connection assignment 0x13 0x0f xpt map 0 control 15 5:0 out 15 [5:0] output 15 connection assign ment 0x14 0x10 xpt map 0 control 16 5:0 out 16 [5:0] output 16 connection assignment 0x15 0x11 xpt map 0 control 17 5:0 out 17 [5:0] output 17 connection assignment 0x16 0x12 xpt map 0 control 18 5:0 out 18 [5:0] output 18 connection assignment 0x17 0x 13 xpt map 0 control 19 5:0 out 19 [5:0] output 19 connection assignment 0x18 0x14 xpt map 0 control 20 5:0 out 20 [5:0] output 20 connection assignment 0x19 0x15 xpt map 0 control 21 5:0 out 21 [5:0] output 21 connection assignment 0x1a 0x16 xpt map 0 control 22 5:0 out 22 [5:0] output 22 connection assignment 0x1b 0x17 xpt map 0 control 23 5:0 out 23 [5:0] output 23 connection assignment 0x1c 0x18 xpt map 0 control 24 5:0 out 24 [5:0] output 24 connection assignment 0x1d 0x19 xpt map 0 control 25 5:0 out 25 [5:0] output 25 connection assignment 0x1e 0x1a xpt map 0 control 26 5:0 out 26 [5:0] output 26 connection assignment 0x1f 0x1b xpt map 0 control 27 5:0 out 27 [5:0] output 27 connection assignment 0x20 0x1c xpt map 0 control 28 5:0 out 28 [5:0 ] output 28 connection assignment 0x21 0x1d xpt map 0 control 29 5:0 out 29 [5:0] output 29 connection assignment 0x22 0x1e xpt map 0 control 30 5:0 out 30 [5:0] output 30 connection assignment 0x23 0x1f xpt map 0 control 31 5:0 out 31 [5:0] output 31 c onnection assignment 0x24 0x20 xpt map 0 control 32 5:0 out 32 [5:0] output 32 connection assignment 0x25 0x21 xpt map 0 control 33 5:0 out 33 [5:0] output 33 connection assignment 0x26 0x22 xpt map 0 control 34 5:0 out 34 [5:0] output 34 connection ass ignment 0x27 0x23 xpt map 0 control 35 5:0 out 35 [5:0] output 35 connection assignment 0x28 0x24 xpt map 0 control 36 5:0 out 36 [5:0] output 36 connection assignment 0x29 0x25 xpt map 0 control 37 5:0 out 37[5:0] output 37 connection assignment 0x2a 0x26 xpt map 0 control 38 5:0 out 38 [5:0] output 38 connection assignment 0x2b 0x27 xpt map 0 control 39 5:0 out 39 [5:0] output 39 connection assignment adn4605 data sheet rev. a | page 40 of 56 address : channel default register name bit s bit name description 0x2c 0x27 xpt map 1 control 0 5:0 out 0 [5:0] output 0 connection assignment 0x2d 0x26 xpt map 1 c ontrol 1 5:0 out 1 [5:0] output 1 connection assignment 0x2e 0x25 xpt map 1 control 2 5:0 out 2 [5:0] output 2 connection assignment 0x2f 0x24 xpt map 1 control 3 5:0 out 3 [5:0] output 3 connection assignment 0x30 0x23 xpt map 1 control 4 5:0 out 4 [5: 0] output 4 connection assignment 0x31 0x22 xpt map 1 control 5 5:0 out 5 [5:0] output 5 connection assignment 0x32 0x21 xpt map 1 control 6 5:0 out 6 [5:0] output 6 connection assignment 0x33 0x20 xpt map 1 control 7 5:0 out 7 [5:0] output 7 connection assignment 0x34 0x1f xpt map 1 control 8 5:0 out 8 [5:0] output 8 connection assignment 0x35 0x1e xpt map 1 control 9 5:0 out 9 [5:0] output 9 connection assignment 0x36 0x1d xpt map 1 control 10 5:0 out 10 [5:0] output 10 connection assignment 0x37 0 x1c xpt map 1 control 11 5:0 out 11 [5:0] output 11 connection assignment 0x38 0x1b xpt map 1 control 12 5:0 out 12 [5:0] output 12 connection assignment 0x39 0x1a xpt map 1 control 13 5:0 out 13 [5:0] output 13 connection assignment 0x3a 0x19 xpt map 1 control 14 5:0 out 14 [5:0] output 14 connection assignment 0x3b 0x18 xpt map 1 control 15 5:0 out 15 [5:0] output 15 connection assignment 0x3c 0x17 xpt map 1 control 16 5:0 out 16 [5:0] output 16 connection assignment 0x3d 0x16 xpt map 1 control 17 5:0 out 17 [5:0] output 17 connection assignment 0x3e 0x15 xpt map 1 control 18 5:0 out 18 [5:0] output 18 connection assignment 0x3f 0x14 xpt map 1 control 19 5:0 out 19 [5:0] output 19 connection assignment 0x40 0x13 xpt map 1 control 20 5:0 out 20 [5: 0] output 20 connection assignment 0x41 0x12 xpt map 1 control 21 5:0 out 21 [5:0] output 21 connection assignment 0x42 0x11 xpt map 1 control 22 5:0 out 22 [5:0] output 22 connection assignment 0x43 0x10 xpt map 1 control 23 5:0 out 23 [5:0] output 23 connection assignment 0x44 0x0f xpt map 1 control 24 5:0 out 24 [5:0] output 24 connection assignment 0x45 0x0e xpt map 1 control 25 5:0 out 25 [5:0] output 25 connection assignment 0x46 0x0d xpt map 1 control 26 5:0 out 26 [5:0] output 26 connection as signment 0x47 0x0c xpt map 1 control 27 5:0 out 27 [5:0] output 27 connection assignment 0x48 0x0b xpt map 1 control 28 5:0 out 28 [5:0] output 28 connection assignment 0x49 0x0a xpt map 1 control 29 5:0 out 29 [5:0] output 29 connection assignment 0x4 a 0x09 xpt map 1 control 30 5:0 out 30 [5:0] output 30 connection assignment 0x4b 0x08 xpt map 1 control 31 5:0 out 31 [5:0] output 31 connection assignment 0x4c 0x07 xpt map 1 control 32 5:0 out 32 [5:0] output 32 connection assignment 0x4d 0x06 xpt ma p 1 control 33 5:0 out 33 [5:0] output 33 connection assignment 0x4e 0x05 xpt map 1 control 34 5:0 out 34 [5:0] output 34 connection assignment 0x4f 0x04 xpt map 1 control 35 5:0 out 35 [5:0] output 35 connection assignment 0x50 0x03 xpt map 1 control 36 5:0 out 36 [5:0] output 36 connection assignment 0x51 0x02 xpt map 1 control 37 5:0 out 37[5:0] output 37 connection assignment 0x52 0x01 xpt map 1 control 38 5:0 out 38 [5:0] output 38 connection assignment 0x53 0x00 xpt map 1 control 39 5:0 out 39 [ 5:0] output 39 connection assignment 0x54 0x00 xpt status 0 5:0 out 0 [5:0] output 0 connection status 0x55 0x00 xpt status 1 5:0 out 1 [5:0] output 1 connection status 0x56 0x00 xpt status 2 5:0 out 2 [5:0] output 2 connection status 0x57 0x00 xpt sta tus 3 5:0 out 3 [5:0] output 3 connection status 0x58 0x00 xpt status 4 5:0 out 4 [5:0] output 4 connection status 0x59 0x00 xpt status 5 5:0 out 5 [5:0] output 5 connection status 0x5a 0x00 xpt status 6 5:0 out 6 [5:0] output 6 connection status 0x5b 0x00 xpt status 7 5:0 out 7 [5:0] output 7 connection status 0x5c 0x00 xpt status 8 5:0 out 8 [5:0] output 8 connection status 0x5d 0x00 xpt status 9 5:0 out 9 [5:0] output 9 connection status 0x5e 0x00 xpt status 10 5:0 out 10 [5:0] output 10 connectio n status 0x5f 0x00 xpt status 11 5:0 out 11 [5:0] output 11 connection status 0x60 0x00 xpt status 12 5:0 out 12 [5:0] output 12 connection status data sheet adn4605 rev. a | page 41 of 56 address : channel default register name bit s bit name description 0x61 0x00 xpt status 13 5:0 out 13 [5:0] output 13 connection status 0x62 0x00 xpt status 14 5:0 out 14 [ 5:0] output 14 connection status 0x63 0x00 xpt status 15 5:0 out 15 [5:0] output 15 connection status 0x64 0x00 xpt status 16 5:0 out 16 [5:0] output 16 connection status 0x65 0x00 xpt status 17 5:0 out 17 [5:0] output 17 connection status 0x66 0x00 xp t status 18 5:0 out 18 [5:0] output 18 connection status 0x67 0x00 xpt status 19 5:0 out 19 [5:0] output 19 connection status 0x68 0x00 xpt status 20 5:0 out 20 [5:0] output 20 connection status 0x69 0x00 xpt status 21 5:0 out 21 [5:0] output 21 connect ion status 0x6a 0x00 xpt status 22 5:0 out 22 [5:0] output 22 connection status 0x6b 0x00 xpt status 23 5:0 out 23 [5:0] output 23 connection status 0x6c 0x00 xpt status 24 5:0 out 24 [5:0] output 24 connection status 0x6d 0x00 xpt status 25 5:0 out 25 [5:0] output 25 connection status 0x6e 0x00 xpt status 26 5:0 out 26 [5:0] output 26 connection status 0x6f 0x00 xpt status 27 5:0 out 27 [5:0] output 27 connection status 0x70 0x00 xpt status 28 5:0 out 28 [5:0] output 28 connection status 0x71 0x00 xpt status 29 5:0 out 29 [5:0] output 29 connection status 0x72 0x00 xpt status 30 5:0 out 30 [5:0] output 30 connection status 0x73 0x00 xpt status 31 5:0 out 31 [5:0] output 31 connection status 0x74 0x00 xpt status 32 5:0 out 32 [5:0] output 32 conne ction status 0x75 0x00 xpt status 33 5:0 out 33 [5:0] output 33 connection status 0x76 0x00 xpt status 34 5:0 out 34 [5:0] output 34 connection status 0x77 0x00 xpt status 35 5:0 out 35 [5:0] output 35 connection status 0x78 0x00 xpt status 36 5:0 out 36 [5:0] output 36 connection status 0x79 0x00 xpt status 37 5:0 out 37[5:0] output 37 connection status 0x7a 0x00 xpt status 38 5:0 out 38 [5:0] output 38 connection status 0x7b 0x00 xpt status 39 5:0 out 39 [5:0] output 39 connection status 0x7d 0x00 xpt headroom 0 xpt_hdroom 0 = d isabled, 1 = e nabled (r equired when v cc > 2.7 v) 0x80: output 0 0x40 t x lane control 7 reserved 0 ( r eserve bit ) 0x81: output 1 0x40 tx lane control 6:4 olev [2:0] 000: 0 ma 0x82: output 2 0x40 tx lane control 001: 4 ma 0x83: output 3 0x40 tx lane control 010: 8 ma 0x84: output 4 0x40 tx lane control 011: 12 ma 0x85: output 5 0x40 tx lane control 100: 16 ma (default) 0x86: output 6 0x40 tx lane control 101: 20 ma 0x87: output 7 0x40 tx lane control 110: 24 ma 0x88: output 8 0x40 tx lane control 111: (reserve bit) 0x89: output 9 0x40 tx lane control 0x8a: output 10 0x40 tx lane control 0x8b: output 11 0x40 tx lane control 3 o verdrive 1: o verdrive (increases olev and pe currents by 25%) 0x8c: out put 12 0x40 tx lane control 0: n o over drive (default) 0x8d: output 13 0x40 tx lane control 0x8e output 14 0x40 tx lane control 0x8f: output 15 0x40 tx lane control 2:0 pe [2:0] 000: 0 ma (default) 0x90: output 16 0x40 tx lane control 001: 2 m a 0x91: output 17 0x40 tx lane control 010: 3 ma 0x92: output 18 0x40 tx lane control 011: 4 ma 0x93: output 19 0x40 tx lane control 100: 5 ma 0x94: output 20 0x40 tx lane control 101: 6 ma 0x95: output 21 0x40 tx lane control 110: 7 ma 0x9 6: output 22 0x40 tx lane control 111: 8 ma 0x97: output 23 0x40 tx lane control 0x98: output 24 0x40 tx lane control adn4605 data sheet rev. a | page 42 of 56 address : channel default register name bit s bit name description 0x99: output 25 0x40 tx lane control 0x9a: output 26 0x40 tx lane control 0x9b: output 27 0x40 tx lane control 0x9c : output 28 0x40 tx lane control 0x9d: output 29 0x40 tx lane control 0x9e: output 30 0x40 tx lane control 0x9f: output 31 0x40 tx lane control 0xa0: output 32 0x40 tx lane control 0xa1: output 33 0x40 tx lane control 0xa2: output 3 4 0x40 tx lane control 0xa3: output 35 0x40 tx lane control 0xa4: output 36 0x40 tx lane control 0xa5: output 37 0x40 tx lane control 0xa6: output 38 0x40 tx lane control 0xa7: output 39 0x40 tx lane control 0xa8: tx broadcast 0x40 tx lane control 0xa9 0x0 tx sign control 7 txsign [7] signal path polarity inversion output 7 0 = n oninverting 1 = i nverting 6 txsign [6] signal path polarity inversion output 6 5 txsign [5] signal path polarity inversion output 5 4 txsign [4] signal path polarity inversion output 4 3 txsign [3] signal path polarity inversion output 3 2 txsign [2] signal path polarity inversion output 2 1 txsign [1] signal path polarity inversion output 1 0 txsign [0] signal path polarity inversion output 0 0xaa 0x0 tx sign control 7 txsign [15] signal path polarity inversion output 15 6 txsign [14] signal path polarity inversion output 14 5 txsign [13] signal path polarity inversion output 13 4 txsign [12] signal path polarity inversion output 12 3 txsign [11] signal path polarity inversion output 11 2 txsign [10] signal path polarity inversion output 10 1 txsign [9] signal path polarity inversion output 9 0 txsign [8] signal path polarity inversion out put 8 0xab 0x0 tx sign control 7 txsign [23] signal path polarity inversion output 23 6 txsign [22] signal path polarity inversion output 22 5 txsign [21] signal path polarity inversion output 21 4 txsign [20] signal path polarity inversion ou tput 20 3 txsign [19] signal path polarity inversion output 19 2 txsign [18] signal path polarity inversion output 18 1 txsign [17] signal path polarity inversion output 17 0 txsign [16] signal path polarity inversion output 16 0xac 0x0 tx sign control 7 txsign [31] signal path polarity inversion output 31 6 txsign [30] signal path polarity inversion output 30 5 txsign [29] signal path polarity inversion output 29 4 txsign [28] signal path polarity inversion output 28 3 txsi gn [27] signal path polarity inversion output 27 2 txsign [26] signal path polarity inversion output 26 1 txsign [25] signal path polarity inversion output 25 0 txsign [24] signal path polarity inversion output 24 data sheet adn4605 rev. a | page 43 of 56 address : channel default register name bit s bit name description 0xad 0x0 tx sign control 7 tx sign [ 39] signal path polarity inversion output 39 6 txsign [ 38] signal path polarity inversion output 38 5 txsign [ 37] signal path polarity inversion output 37 4 txsign [ 36] signal path polarity inversion output 36 3 txsign [ 35] signal pat h polarity inversion output 35 2 txsign [ 34] signal path polarity inversion output 34 1 txsign [33] signal path polarity inversion output 33 0 txsign [ 32] signal path polarity inversion output 32 0xb0 0x0 tx drive control 7:6 txen [3] tx enabl e state output 3 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [ 2] tx enable state output 2 3:2 txen [ 1] tx enable state output 1 1:0 txen [ 0] tx enable state output 0 0xb1 0x0 tx drive control 7:6 txen [ 7] tx enable state output 7 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [ 6] tx enable state output 6 3:2 txen [ 5] tx enable state output 5 1:0 txen [ 4] tx enable state output 4 0xb2 0x0 tx drive contr ol 7:6 txen [ 11] tx enable state output 11 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [ 10] tx enable state output 10 3:2 txen [ 9] tx enable state output 9 1:0 txen [ 8] tx enable state output 8 0xb3 0x 0 tx drive control 7:6 txen [ 15] tx enable state output 15 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [14] tx enable state output 14 3:2 txen [13] tx enable state output 13 1:0 txen [12] tx enable stat e output 12 0xb4 0x0 tx drive control 7:6 txen [19] tx enable state output 19 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [18] tx enable state output 18 3:2 txen [17] tx enable state output 17 1:0 txen [16] tx enable state output 16 adn4605 data sheet rev. a | page 44 of 56 address : channel default register name bit s bit name description 0xb5 0x0 tx drive control 7:6 txen [23] tx enable state output 23 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [22] tx enable state output 22 3:2 txen [21] tx enable state ou tput 21 1:0 txen [20] tx enable state output 20 0xb6 0x0 tx drive control 7:6 txen [27] tx enable state output 27 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [26] tx enable state output 26 3:2 txen [25 ] tx enable state output 25 1:0 txen [24] tx enable state output 24 0xb7 0x0 tx drive control 7:6 txen [31] tx enable state output 31 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [30] tx enable state output 30 3:2 txen [29] tx enable state output 29 1:0 txen [28] tx enable state output 28 0xb8 0x0 tx drive control 7:6 txen [35] tx enable state output 35 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [34] tx enable state output 34 3:2 txen [33] tx enable state output 33 1:0 txen [32] tx enable state output 32 0xb9 0x0 tx drive control 7:6 txen [39] tx enable state output 39 11 = enabled 10 = standby 01 = squelch 00 = disabled 5:4 txen [38] tx enable state output 38 3:2 txen [37] tx enable state output 37 1:0 txen [36] tx enable state output 36 0xba write only tx drive control 7:6 txenbc [39] tx enable state broadcast 11 = enabled 10 = standby 01 = squelch 00 = d isabled 0xbb 0x0 t x headroom 0 tx_hdroom 0 = disabled, 1 = enabled (required when v cc > 2.7 v) data sheet adn4605 rev. a | page 45 of 56 address : channel default register name bit s bit name description 0xbc 0x0 t x termination 4 tx a _term [19:16] output[19:16] (b s ide) termination control c ontrol 0: terminations enabled 1: termin ations disabled 3 tx a _term [15:12] output[15:12] (b s ide) termination control 2 tx a _term [11:8] output[11:8] (b s ide) termination control 1 tx a _term [7:4] output[7:4] (b s ide) termination control 0 txa_term [3:0] output[3:0] (b side) termin ation control 0xbd 0x0 t x termination 4 tx b _term [39:36] output[39:36] (b s ide) termination contro l control 0: terminations enabled 1: terminations disabled 3 tx b _term [35:32] output[35:32] (b s ide) termination control 2 tx b _term [31:2 8] output[31:28] (b s ide) termination control 1 tx b _term [27:24] output[27:24] (b s ide) termination control 0 tx b _term [23:20] output[23:20] (b s ide) termination control 0xc0 0x0 r x eq control 7:6 rxeqin [3] equalizer boost control for input 3 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [2] equalizer boost control for input 2 3:2 rxeqin [1] equalizer boost control for input 1 1:0 rxeqin [0] equalizer boost control for input 0 0xc1 0x0 r x eq control 7:6 rxeqin [7] equalizer boost control for input 7 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [6] equalizer boost control for input 6 3:2 rxeqin [5] equalizer boost control for input 5 1:0 rxeqin [4] equalize r boost control for input 4 0xc2 0x0 r x eq control 7:6 rxeqin [11] equalizer boost control for input 11 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [10] equalizer boost control for input 10 3:2 rxeqin [9] equali zer boost control for input 9 1:0 rxeqin [8] equalizer boost control for input 8 0xc3 0x0 r x eq control 7:6 rxeqin [15] equalizer boost control for input 15 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [14] equal izer boost control for input 14 3:2 rxeqin [13] equalizer boost control for input 13 1:0 rxeqin [12] equalizer boost control for input 12 adn4605 data sheet rev. a | page 46 of 5 6 address : channel default register name bit s bit name description 0xc4 0x0 r x eq control 7:6 rxeqin [19] equalizer boost control for input 19 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [18] equalizer boost control for input 18 3:2 rxeqin [17] equalizer boost control for input 17 1:0 rxeqin [16] equalizer boost control for input 16 0xc5 0x0 r x eq control 7:6 rxeqin [23] equalizer boost control for input 23 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [22] equalizer boost control for input 22 3:2 rxeqin [21] equalizer boost control for input 21 1:0 rxeqin [20] equalizer boost control f or input 20 0xc6 0x0 r x eq control 7:6 rxeqin [27] equalizer boost control for input 27 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [26] equalizer boost control for input 26 3:2 rxeqin [25] equalizer boost contr ol for input 25 1:0 rxeqin [24] equalizer boost control for input 24 0xc7 0x0 r x eq control 7:6 rxeqin [31] equalizer boost control for input 31 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [30] equalizer boost c ontrol for input 30 3:2 rxeqin [29] equalizer boost control for input 29 1:0 rxeqin [28] equalizer boost control for input 28 0xc8 0x0 r x eq control 7:6 rxeqin [35] equalizer boost control for input 35 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [34] equalizer boost control for input 34 3:2 rxeqin [33] equalizer boost control for input 33 1:0 rxeqin [32] equalizer boost control for input 32 0xc9 0x0 r x eq control 7:6 rxeqin [39] equalizer boost contr ol for input 39 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled 5:4 rxeqin [38] equalizer boost control for input 38 3:2 rxeqin [37] equalizer boost control for input 37 1:0 rxeqin [36] equalizer boost control for input 36 0xca 0x0 r x eq control 1:0 rxeqin bc equalizer boost control for all inputs 11 = 12 db 10 = 6 db 01 = 3 db 00 = d isabled data sheet adn4605 rev. a | page 47 of 56 address : channel default register name bit s bit name description 0xcb 0x0 r x s ign control 7 rxsign [7] signal path polarity inversion input 7 6 rxsign [6] signal path pol arity inversion input 6 5 rxsign [5] signal path polarity inversion input 5 4 rxsign [4] signal path polarity inversion input 4 3 rxsign [3] signal path polarity inversion input 3 2 rxsign [2] signal path polarity inversion input 2 1 rx sign [1] signal path polarity inversion input 1 0 rxsign [0] signal path polarity inversion input 0 0xcc 0x0 rx sign control 7 rxsign [15] signal path polarity inversion input 15 6 rxsign [14] signal path polarity inversion input 14 5 rxsign [ 13] signal path polarity inversion input 13 4 rxsign [12] signal path polarity inversion input 12 3 rxsign [11] signal path polarity inversion input 11 2 rxsign [10] signal path polarity inversion input 10 1 rxsign [9] signal path polarity inversion input 9 0 rxsign [8] signal path polarity inversion input 8 0xcd 0x0 rx sign control 7 rxsign [23] signal path polarity inversion input 23 6 rxsign [22] signal path polarity inversion input 22 5 rxsign [21] signal path polarity inver sion input 21 4 rxsign [20] signal path polarity inversion input 20 3 rxsign [19] signal path polarity inversion input 19 2 rxsign [18] signal path polarity inversion input 18 1 rxsign [17] signal path polarity inversion input 17 0 rxsi gn [16] signal path polarity inversion input 16 0xce 0x0 rx sign control 7 rxsign [31] signal path polarity inversion input 31 6 rxsign [30] signal path polarity inversion input 30 5 rxsign [29] signal path polarity inversion input 29 4 rxsign [28] signal path polarity inversion input 28 3 rxsign [27] signal path polarity inversion input 27 2 rxsign [26] signal path polarity inversion input 26 1 rxsign [25] signal path polarity inversion input 25 0 rxsign [24] signal path polari ty inversion input 24 0xcf 0x0 rx sign control 7 rxsign [39] signal path polarity inversion input 39 6 rxsign [38] signal path polarity inversion input 38 5 rxsign [37] signal path polarity inversion input 37 4 rxsign [36] signal path polarity inversion input 36 3 rxsign [35] signal path polarity inversion input 35 2 rxsign [34] signal path polarity inversion input 34 1 rxsign [33] signal path polarity inversion input 33 0 rxsign [32] signal path polarity inversion input 32 0xd 0 0x0 r x termination 4 rx a _term [19:16] input[19:16] (a side) termination control control 0: termination control enabled 1: termination control disabled 3 rx a _term [15:12] input [15:12] ( a s ide ) termination control 2 rx a _term [11:8] inpu t [11:8] ( a s ide ) termination control 1 rx a _term [7:4] input [7:4] ( a s ide ) termination control 0 rx a _term [3:0] input [3:0] ( a s ide ) termination control adn4605 data sheet rev. a | page 48 of 56 address : channel default register name bit s bit name description 0xd1 0x0 r x termination 4 rx b _term [39:36] input [39:36] ( b side ) termination control cont rol 0: t erminations enabled 1: t erminations disabled 3 rx b _term [35:32] input [35:32] ( b side ) termination control 2 rx b _term [31:28] input [31:28] ( b side ) termination control 1 rx b _term [27:24] input [27:24] ( b side ) termination contr ol 0 rx b _term [23:20] input [23:20] ( b side ) termination control data sheet adn4605 rev. a | page 49 of 56 applications informa tion the adn460 5 is an asynchronous and protocol agnostic digital switch and, therefore, is applicable to a wide range of applica - tions including network routing and digital video switching. the adn460 5 supports the data rates and signaling levels of hdmi?, dvi?, displayport and sd - , hd - , and 3g - sdi digital video. the adn460 5 can be used to create matrix switches. an example block diagram of a 40 40 matrix switch is shown in figure 50 . since hdmi, dvi, and displayport are quad lane protocols, four adn460 5 s are used to create a full 40 40 matrix switch. smaller arrays, such as 10 10 and 20 20, require one and two adn460 5 devices , respectively. proper high speed pcb design techniques should be used to maintain the signal integrity of the high data rate signals. it is important to minimize the lane - to - lane skew and crosstalk in these applications. adn4605 in 0 in 1 in 39 out 0 out 1 out 39 adn4605 in 0 in 1 in 39 out 0 out 1 out 39 adn4605 in 0 in 1 in 39 out 0 out 1 out 39 adn4605 in 0 in 1 in 39 out 0 out 1 out 39 source 1 source 2 source 40 source 39 displ a y 1 displ a y 2 displ a y 40 displ a y 39 09796-052 figure 50 . adn460 5 digital video (dvi, hdmi, displayport) matrix switch block diagram adn4605 data sheet rev. a | page 50 of 56 o/e o/e e/o e/o cdr cdr o/e e/o cdr adn4605 40 40 crosspoint switch in 1 in 2 in 39 out 1 out 2 out 39 09796-053 figure 51 . adn460 5 networking switch application block diagram pe eq loss y channe l 8 lane uplink pa th 8 lane downlink pa th loss y channe l asic 2 eq pe asic 1 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 07934-053 figure 52 . multil ane signal conditioning appl ication diagram data sheet adn4605 rev. a | page 51 of 56 supply sequencing ideally, all power supplies should be brought up to the appropri - ate levels simultaneously (power supply requirements are set by the supply limits in table 1 and the absolute maximum ratings li sted i n table 6 ). if the power supplies to the adn460 5 are brought up separately, the supply power - up sequence is as follows: dv cc powered first, followed by v cc , and, last the termination supplies (v tti a , v tti b , v tto a , and v tto b ). the power - down sequence is reversed with termination supplies being powered off first. the termination supplies contain esd protection diodes to the v cc power domain. to avoid a sustained high curr ent condition in these devices , the v tti x and v tto x supplies should be powered on after v cc and should be powered off before v cc . if the system power supplies have a high impedance in the powered off state, then supply sequencing is not required provided the following limits are observed: ? peak current from v tti x or v tto x to v cc < 200 ma ? sustained current from v tti x or v tto x to v cc < 100 ma power dissipation the power dissipation of the adn460 5 depends on the supply voltages, i/o coupling type, and de vice configuration. the input termination resistors dissipate power depending on the differential input swing and common - mode voltage. when ac - coupled, the common - mode voltage is equal to the termination supply voltage (v tti x or v tto x ). while the current d rawn from the input termination supply is effectively zero, there is still power and heat dissipated in the termination resistors as a result of the differential signal swing. the core supply current and output termination current are strongly dependent on device configuration, such as the number of channels enabled, output level setting, and output preemphasis setting. in high ambient temperature operating conditions, it is impor - tant to avoid exceeding the maximum junction temperature of the device. lim iting the total power dissipation can be achieved by the following: ? reducing the output swing ? reducing the preemphasis level ? decreasing the supply voltages within the allowable ranges defined in table 1 ? disabling unused channels alternatively, the thermal resistance can be reduced by ? adding an external heat sink ? increasing the airflow refer to the printed circuit board (pcb) layout guidelines section for recommendations for proper thermal stencil layout a nd fabrication. output compliance in low voltage applications, users must pay careful attention to both the differential and common - mode signal level s . the choice of output voltage swing, preemphasis setting, supply voltages (v cc and v tto x ), and output co upling (ac or dc) affect peak and settled single - ended voltage swings and the common - mode shift measured across the output termination resistors. these choices also affect output current and, consequently, power consumption. table 20 shows the change in output common mode (v ocm = v cc ? v ocm ) with output level and preemphasis setting. single - ended output levels are calculated for v tto x supplies of 3.3 v and 2.5 v to illustrate practical challenges of reducing the supply voltage. the m inimum v l (min v l ) cannot be below the absolute minimum level specified in table 1 . since the absolute minimum output voltage specified in tabl e 1 is relative to v cc , decreasing v cc is required to mainta in the output levels within the specified limits when lower output termination voltages are required. v tto x voltages as low as 1.8 v are allowable for output swings less than or equal to 400 mv (single - ended). figure 53 illustrat es an application where the adn460 5 is used as a dc - coupled leve l translator to interface a 3.3 v cml driver to an asic with 1.8 v i/os. the diode in series with v cc reduces the voltage at v cc for improved output compliance. tx /xpt headroom the t x headroom and xpt headroom registers are provided to improve the output compliance range of the adn4605 when the core supply voltage (v cc ) is greater than 2.7 v. enabling the xpt headroom and t x headroom registers a ll ows the transmitter an extra 3 00 mv of output compliance. t he headroom circuitry should not be enabled when the core supply voltage ( v cc ) is les s than or equal to 2.7 v. when set to 1, t he xpt h eadroom (address 0x7d) and tx h eadroom (address 0x bb) regist ers are enabled for all transmitter outputs. a value of 0 disables the headroom generating circuitry. note that both registers (xpt h eadroom and tx h eadroom ) must be set for the headroom circuitry to function properly. adn4605 data sheet rev. a | page 52 of 56 example : v cc = 3.3 v, v tto x = 2.5 v in a typical application, the user can select a default output level of 200 mv single - ended (400 mvp - p differential) and may want the option to choose pr eemphasis settings of 0 db and 9.5 db. with preemphasis disabled, a dc - coupled transmitter causes a 1 00 mv common - mode shift across the termination resistors, whereas an ac - coupled transmitter causes twice the common - mode shift. when dc - coupled , the single - ended output voltage swings between 2.5 v and 2.3 v and between 2.4 v and 2.2 v when ac - coupled. in both cases, these levels are greater than the minimum v l limit of 1.9 v (v l = v cc ? 1.4 v). with a pe setting of 9.5 db, the ac - coupled transmitter has single - ended swings from 2.2 v and 1.6 v, whereas the dc - coupled transmitter outputs swing between 2.5 v and 1.9 v. the minimum single - ended output voltage (v l - pe ) of t he ac - coupled transmit ter case exceeds the minimum v l limit of 1.9 v by 300 mv, viola ting the device specification. enabling the tx _hdroom and xpt _hdroom bit lower s the minimum v l limit by approximately 300 mv to 1.6 v. this transmitter configuration now complies with the output voltage range specification . data sheet adn4605 rev. a | page 53 of 56 cm l v ee v tt ox 1.8v 1.8v 3.3v 3.3v v cc v ttix adn4605 cm l 3.3v z 0 z 0 z 0 z 0 asic rx 09796-055 figure 53 . dc - coupled level translator application circuit table 20. output volta ge range and output common - mode shift vs. output level and pe setting single - ended output levels and pe boost tx lane control register settings output current ac - coupled outputs dc - coupled outputs v cc = v tto = 3.3 v v cc = v tto = 2.5 v v cc = v tto = 3.3 v v cc = v tto = 2.5 v v sw - dc 1 (mv) v sw - pe 1 (mv) pe boost % pe (db) olev [2:0] pe [2:0] i tto 1 (ma) ?v ocm 1 (mv) v h - pe 1 (v) v l - pe 1 (v) v h - pe 1 (v) v l - pe 1 (v) ?v ocm 1 (mv) v h - pe 1 (v) v l - pe 1 (v) v h - pe 1 (v) v l - pe 1 (v) 100 100 0.00 0.00 0x 0 1 0x00 4 100 3.25 3.15 2.45 2.35 50 3.3 3.2 2.5 2.4 100 300 200.00 9.54 0x02 0x03 12 300 3.15 2.85 2.35 2.05 150 3.3 3.0 2.5 2.2 100 500 400.00 13.98 0x03 0x07 20 500 3.05 2.55 2.25 1.75 250 3.3 2.8 2.5 2.0 150 250 66.67 4.44 0x02 0x01 10 250 3.175 2.925 2.375 2.125 125 3.3 3.15 2.5 2.25 150 450 200.00 9.54 0x03 0x05 18 450 3.075 2.625 2.275 1.825 225 3.3 2.85 2.5 2.05 200 200 0.00 0.00 0x02 0x00 8 200 3.2 3.0 2. 40 2.20 100 3.3 3.1 2.5 2.3 200 400 100.00 6.02 0x03 0x03 16 400 3.1 2.7 2.30 1.90 200 3.3 2.9 2.5 2.1 200 600 200.00 9.54 0x04 0x07 24 600 3 2.4 2.20 1.60 300 3.3 2.7 2.5 1.9 250 350 40.00 2.92 0x03 0x01 14 350 3.125 2.775 2.325 1.975 175 3.3 2.95 2.5 2.15 250 5 50 200.00 6.85 0x04 0x05 22 550 3.025 2.475 2.225 1.675 275 3.3 2.75 2.5 1.95 300 300 0.00 0.00 0x03 0x00 12 300 3.15 2.85 2.35 2.05 150 3.3 3.0 2.5 2.2 300 500 66.67 4.44 0x04 0x03 20 500 3.05 2.55 2.25 1.75 250 3.3 2.8 2.5 2.0 300 700 133.3 3 7.36 0x05 0x07 28 700 2.95 2.25 2.15 1.45 350 3.3 2.6 2.5 1.8 350 450 28.57 2.18 0x04 0x01 18 450 3.075 2.625 2.275 1.825 225 3.3 2.85 2.5 2.05 350 650 85.71 5.38 0x05 0x05 26 650 2.975 2.325 2.175 1.525 325 3.3 2.65 2.5 1.85 400 400 0.00 0.00 0x04 0x 00 16 400 3.1 2.7 2.3 1.9 200 3.3 2.9 2.5 2.1 400 600 50.00 3.52 0x05 0x03 24 600 3.0 2.4 2.2 1.6 300 3.3 2.7 2.5 1.9 400 800 100.00 6.02 0x06 0x07 32 800 2.9 2.1 2.1 1.3 400 3.3 2.5 2.5 1.7 450 550 22.22 1.74 0x05 0x01 22 550 3.025 2.475 2.225 1.675 275 3.3 2.75 2.5 1.95 450 750 66.67 4.44 0x06 0x05 30 750 2.925 2.175 2.125 1.375 375 3.3 2.55 2.5 1.75 500 500 0.00 0.00 0x05 0x00 20 500 3.05 2.55 2.25 1.75 250 3.3 2.8 2.5 2.0 500 700 40.00 2.92 0x06 0x03 28 700 2.95 2.25 2.15 1.45 350 3.3 2.6 2.5 1.8 550 650 18.18 1.45 0x06 0x01 26 650 2.975 2.325 2.175 1.525 325 3.3 2.65 2.5 1.85 600 600 0.00 0.00 0x06 0x00 24 600 3.0 2.4 2.2 1.6 300 3.3 2.7 2.5 1.9 1 symbol definitions are shown in table 15. adn4605 data sheet rev. a | page 54 of 56 printed circuit boar d (pcb) layout guidelines the high speed differential inputs and outputs should be routed with 100 controlled impedance differential transmission lines. the transmission lines, either microstrip or stripline, should be referenced to a solid low impedance refere nce plane. an example of a pcb cross - section is shown in figure 54 . the trace width (w), differential spacing (s), height above reference plane (h), and dielectric constant of the pcb material determine the characteristic impedanc e. adjacent channels should be kept apart by a distance greater than 3 w to minimize crosstalk. pcb dielectric signal (microstrip) soldermask pcb dielectric pcb dielectric pcb dielectric reference plane reference plane signal (stripline) w s w h w s w 09796-100 figure 54 . example of a pcb cross - section adn4605 data sheet rev. a | page 55 of 56 outline dimensions detail a 1.27 bsc a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 4 6 8 10 12 3 5 7 9 11 2 16 18 20 22 15 17 19 21 23 14 13 24 25 26 31.85 31.75 sq 31.65 35.10 35.00 sq 34.90 ball a1 indicator top view bottom view a1 corner index area 0.20 min 0.70 0.60 0.50 1.00 0.80 0.60 coplanarity 0.35 0.90 0.75 0.60 seating plane ba ll diameter detail a 1.70 max compliant to jedec standards mo-192-bal-2 022206- a 0.25 min ( 4 ) figure 55 . 352 - ball grid array, thermally enhanced [bga_ed] (bp - 352) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad n4605a bp z ? 40c to +85c 352- ball ball grid array, thermally enhanced [bga_ed] bp -352 ad n4605- evalz evaluation board 1 z = r o hs compliant part. adn4605 data sheet rev. a | page 56 of 56 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). hdmi, the hdmi logo, and high - definition multimedia interface are tradem arks or registered trademarks of hdmi licensing llc in the united states and other countries. ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09796 - 0- 11/11(a) |
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